{"id":"https://openalex.org/W2156662023","doi":"https://doi.org/10.1145/1531542.1531587","title":"Moebius circuit","display_name":"Moebius circuit","publication_year":2009,"publication_date":"2009-05-10","ids":{"openalex":"https://openalex.org/W2156662023","doi":"https://doi.org/10.1145/1531542.1531587","mag":"2156662023"},"language":"en","primary_location":{"id":"doi:10.1145/1531542.1531587","is_oa":false,"landing_page_url":"https://doi.org/10.1145/1531542.1531587","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 19th ACM Great Lakes symposium on VLSI","raw_type":"proceedings-article"},"type":"conference-paper","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5035293063","display_name":"MyeongGyu Jeong","orcid":null},"institutions":[{"id":"https://openalex.org/I74801974","display_name":"The University of Tokyo","ror":"https://ror.org/057zh3y96","country_code":"JP","type":"education","lineage":["https://openalex.org/I74801974"]}],"countries":["JP"],"is_corresponding":false,"raw_author_name":"MyeongGyu Jeong","raw_affiliation_strings":["The University of Tokyo, Tokyo, Japan"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"The University of Tokyo, Tokyo, Japan","institution_ids":["https://openalex.org/I74801974"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5071803491","display_name":"Toru Nakura","orcid":"https://orcid.org/0000-0001-5945-3918"},"institutions":[{"id":"https://openalex.org/I74801974","display_name":"The University of Tokyo","ror":"https://ror.org/057zh3y96","country_code":"JP","type":"education","lineage":["https://openalex.org/I74801974"]}],"countries":["JP"],"is_corresponding":false,"raw_author_name":"Toru Nakura","raw_affiliation_strings":["The University of Tokyo, Tokyo, Japan"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"The University of Tokyo, Tokyo, Japan","institution_ids":["https://openalex.org/I74801974"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5102900006","display_name":"Makoto Ikeda","orcid":"https://orcid.org/0000-0002-6644-4224"},"institutions":[{"id":"https://openalex.org/I74801974","display_name":"The University of Tokyo","ror":"https://ror.org/057zh3y96","country_code":"JP","type":"education","lineage":["https://openalex.org/I74801974"]}],"countries":["JP"],"is_corresponding":false,"raw_author_name":"Makoto Ikeda","raw_affiliation_strings":["The University of Tokyo, Tokyo, Japan"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"The University of Tokyo, Tokyo, Japan","institution_ids":["https://openalex.org/I74801974"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5028680447","display_name":"Kunihiro Asada","orcid":"https://orcid.org/0000-0002-1150-0241"},"institutions":[{"id":"https://openalex.org/I74801974","display_name":"The University of Tokyo","ror":"https://ror.org/057zh3y96","country_code":"JP","type":"education","lineage":["https://openalex.org/I74801974"]}],"countries":["JP"],"is_corresponding":false,"raw_author_name":"Kunihiro Asada","raw_affiliation_strings":["The University of Tokyo, Tokyo, Japan"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"The University of Tokyo, Tokyo, Japan","institution_ids":["https://openalex.org/I74801974"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":1,"corresponding_author_ids":[],"corresponding_institution_ids":["https://openalex.org/I74801974"],"apc_list":null,"apc_paid":null,"fwci":null,"has_fulltext":false,"cited_by_count":11,"citation_normalized_percentile":null,"cited_by_percentile_year":null,"biblio":{"volume":null,"issue":null,"first_page":"177","last_page":"180"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10558","display_name":"Advancements in Semiconductor Devices and Circuit Design","score":0.9945999979972839,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10558","display_name":"Advancements in Semiconductor Devices and Circuit Design","score":0.9945999979972839,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9936000108718872,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10472","display_name":"Semiconductor materials and devices","score":0.9832000136375427,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/pipeline","display_name":"Pipeline (software)","score":0.7213950753211975},{"id":"https://openalex.org/keywords/logic-gate","display_name":"Logic gate","score":0.6745659112930298},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.664169430732727},{"id":"https://openalex.org/keywords/digital-electronics","display_name":"Digital electronics","score":0.5134118795394897},{"id":"https://openalex.org/keywords/logic-synthesis","display_name":"Logic synthesis","score":0.5061189532279968},{"id":"https://openalex.org/keywords/register-transfer-level","display_name":"Register-transfer level","score":0.49372753500938416},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.476641982793808},{"id":"https://openalex.org/keywords/logic-optimization","display_name":"Logic optimization","score":0.4667048454284668},{"id":"https://openalex.org/keywords/circuit-complexity","display_name":"Circuit complexity","score":0.46533456444740295},{"id":"https://openalex.org/keywords/pass-transistor-logic","display_name":"Pass transistor logic","score":0.4539759159088135},{"id":"https://openalex.org/keywords/inverter","display_name":"Inverter","score":0.4406295716762543},{"id":"https://openalex.org/keywords/throughput","display_name":"Throughput","score":0.4351550340652466},{"id":"https://openalex.org/keywords/electronic-circuit","display_name":"Electronic circuit","score":0.39872056245803833},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.3347170948982239},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.22954213619232178},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.19526973366737366},{"id":"https://openalex.org/keywords/voltage","display_name":"Voltage","score":0.14138880372047424},{"id":"https://openalex.org/keywords/telecommunications","display_name":"Telecommunications","score":0.08296903967857361}],"concepts":[{"id":"https://openalex.org/C43521106","wikidata":"https://www.wikidata.org/wiki/Q2165493","display_name":"Pipeline (software)","level":2,"score":0.7213950753211975},{"id":"https://openalex.org/C131017901","wikidata":"https://www.wikidata.org/wiki/Q170451","display_name":"Logic gate","level":2,"score":0.6745659112930298},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.664169430732727},{"id":"https://openalex.org/C81843906","wikidata":"https://www.wikidata.org/wiki/Q173156","display_name":"Digital electronics","level":3,"score":0.5134118795394897},{"id":"https://openalex.org/C157922185","wikidata":"https://www.wikidata.org/wiki/Q173198","display_name":"Logic synthesis","level":3,"score":0.5061189532279968},{"id":"https://openalex.org/C34854456","wikidata":"https://www.wikidata.org/wiki/Q1484552","display_name":"Register-transfer level","level":4,"score":0.49372753500938416},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.476641982793808},{"id":"https://openalex.org/C28449271","wikidata":"https://www.wikidata.org/wiki/Q6667469","display_name":"Logic optimization","level":4,"score":0.4667048454284668},{"id":"https://openalex.org/C90702460","wikidata":"https://www.wikidata.org/wiki/Q1055112","display_name":"Circuit complexity","level":3,"score":0.46533456444740295},{"id":"https://openalex.org/C198521697","wikidata":"https://www.wikidata.org/wiki/Q7142438","display_name":"Pass transistor logic","level":4,"score":0.4539759159088135},{"id":"https://openalex.org/C11190779","wikidata":"https://www.wikidata.org/wiki/Q664575","display_name":"Inverter","level":3,"score":0.4406295716762543},{"id":"https://openalex.org/C157764524","wikidata":"https://www.wikidata.org/wiki/Q1383412","display_name":"Throughput","level":3,"score":0.4351550340652466},{"id":"https://openalex.org/C134146338","wikidata":"https://www.wikidata.org/wiki/Q1815901","display_name":"Electronic circuit","level":2,"score":0.39872056245803833},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.3347170948982239},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.22954213619232178},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.19526973366737366},{"id":"https://openalex.org/C165801399","wikidata":"https://www.wikidata.org/wiki/Q25428","display_name":"Voltage","level":2,"score":0.14138880372047424},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.08296903967857361},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.0},{"id":"https://openalex.org/C555944384","wikidata":"https://www.wikidata.org/wiki/Q249","display_name":"Wireless","level":2,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1145/1531542.1531587","is_oa":false,"landing_page_url":"https://doi.org/10.1145/1531542.1531587","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 19th ACM Great Lakes symposium on VLSI","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":3,"referenced_works":["https://openalex.org/W1819724419","https://openalex.org/W2100759575","https://openalex.org/W2143310750"],"related_works":["https://openalex.org/W2373127312","https://openalex.org/W2386022279","https://openalex.org/W2098419840","https://openalex.org/W659242671","https://openalex.org/W2364534035","https://openalex.org/W2377041390","https://openalex.org/W2181841040","https://openalex.org/W2351310008","https://openalex.org/W1965949818","https://openalex.org/W2063209251"],"abstract_inverted_index":{"We":[0],"have":[1],"introduced":[2],"the":[3,6],"concept":[4],"of":[5,20],"Moebius":[7,25],"strip":[8],"into":[9],"LSI":[10],"circuit":[11,26],"design,":[12],"realizing":[13],"8.4":[14],"FO4-Inverter":[15],"throughput":[16],"for":[17],"any":[18],"kind":[19],"digital":[21],"logic":[22,30],"circuit.":[23],"The":[24],"operates":[27],"in":[28],"a":[29,44],"gate":[31,40],"level":[32],"pipeline,":[33],"and":[34,38],"has":[35],"error":[36,39],"detection":[37],"search":[41],"features,":[42],"using":[43],"self-timed":[45],"architecture.":[46]},"counts_by_year":[{"year":2015,"cited_by_count":2},{"year":2014,"cited_by_count":1},{"year":2013,"cited_by_count":2},{"year":2012,"cited_by_count":2}],"updated_date":"2026-07-14T23:27:15.235271","created_date":"2016-06-24T00:00:00"}