{"id":"https://openalex.org/W2032842232","doi":"https://doi.org/10.1145/1514932.1514964","title":"An algorithm for routing with capacitance/distance constraints for clock distribution in microprocessors","display_name":"An algorithm for routing with capacitance/distance constraints for clock distribution in microprocessors","publication_year":2009,"publication_date":"2009-03-29","ids":{"openalex":"https://openalex.org/W2032842232","doi":"https://doi.org/10.1145/1514932.1514964","mag":"2032842232"},"language":"en","primary_location":{"id":"doi:10.1145/1514932.1514964","is_oa":false,"landing_page_url":"https://doi.org/10.1145/1514932.1514964","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 2009 international symposium on Physical design","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5029632511","display_name":"Rupesh S. Shelar","orcid":null},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":true,"raw_author_name":"Rupesh S. Shelar","raw_affiliation_strings":["Intel Corporation, Hillsboro, OR, USA","Intel Corporation, , Hillsboro, OR, USA"],"affiliations":[{"raw_affiliation_string":"Intel Corporation, Hillsboro, OR, USA","institution_ids":["https://openalex.org/I1343180700"]},{"raw_affiliation_string":"Intel Corporation, , Hillsboro, OR, USA","institution_ids":["https://openalex.org/I1343180700"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":1,"corresponding_author_ids":["https://openalex.org/A5029632511"],"corresponding_institution_ids":["https://openalex.org/I1343180700"],"apc_list":null,"apc_paid":null,"fwci":4.7852,"has_fulltext":false,"cited_by_count":20,"citation_normalized_percentile":{"value":0.94993569,"is_in_top_1_percent":false,"is_in_top_10_percent":true},"cited_by_percentile_year":{"min":89,"max":97},"biblio":{"volume":null,"issue":null,"first_page":"141","last_page":"148"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9995999932289124,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9994999766349792,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/capacitance","display_name":"Capacitance","score":0.6974479556083679},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.6215375065803528},{"id":"https://openalex.org/keywords/routing","display_name":"Routing (electronic design automation)","score":0.6175085306167603},{"id":"https://openalex.org/keywords/grid","display_name":"Grid","score":0.5551441311836243},{"id":"https://openalex.org/keywords/block","display_name":"Block (permutation group theory)","score":0.496542751789093},{"id":"https://openalex.org/keywords/skew","display_name":"Skew","score":0.4960993230342865},{"id":"https://openalex.org/keywords/placement","display_name":"Placement","score":0.48805439472198486},{"id":"https://openalex.org/keywords/microprocessor","display_name":"Microprocessor","score":0.4597165584564209},{"id":"https://openalex.org/keywords/heuristic","display_name":"Heuristic","score":0.4463490843772888},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.4152528643608093},{"id":"https://openalex.org/keywords/place-and-route","display_name":"Place and route","score":0.41302186250686646},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.39181628823280334},{"id":"https://openalex.org/keywords/mathematics","display_name":"Mathematics","score":0.1898331642150879},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.18533474206924438},{"id":"https://openalex.org/keywords/physical-design","display_name":"Physical design","score":0.17401790618896484},{"id":"https://openalex.org/keywords/computer-network","display_name":"Computer network","score":0.1639707088470459},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.1566089689731598},{"id":"https://openalex.org/keywords/telecommunications","display_name":"Telecommunications","score":0.09258297085762024},{"id":"https://openalex.org/keywords/circuit-design","display_name":"Circuit design","score":0.07564595341682434}],"concepts":[{"id":"https://openalex.org/C30066665","wikidata":"https://www.wikidata.org/wiki/Q164399","display_name":"Capacitance","level":3,"score":0.6974479556083679},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6215375065803528},{"id":"https://openalex.org/C74172769","wikidata":"https://www.wikidata.org/wiki/Q1446839","display_name":"Routing (electronic design automation)","level":2,"score":0.6175085306167603},{"id":"https://openalex.org/C187691185","wikidata":"https://www.wikidata.org/wiki/Q2020720","display_name":"Grid","level":2,"score":0.5551441311836243},{"id":"https://openalex.org/C2777210771","wikidata":"https://www.wikidata.org/wiki/Q4927124","display_name":"Block (permutation group theory)","level":2,"score":0.496542751789093},{"id":"https://openalex.org/C43711488","wikidata":"https://www.wikidata.org/wiki/Q7534783","display_name":"Skew","level":2,"score":0.4960993230342865},{"id":"https://openalex.org/C117690923","wikidata":"https://www.wikidata.org/wiki/Q1484784","display_name":"Placement","level":4,"score":0.48805439472198486},{"id":"https://openalex.org/C2780728072","wikidata":"https://www.wikidata.org/wiki/Q5297","display_name":"Microprocessor","level":2,"score":0.4597165584564209},{"id":"https://openalex.org/C173801870","wikidata":"https://www.wikidata.org/wiki/Q201413","display_name":"Heuristic","level":2,"score":0.4463490843772888},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.4152528643608093},{"id":"https://openalex.org/C127879752","wikidata":"https://www.wikidata.org/wiki/Q3390760","display_name":"Place and route","level":3,"score":0.41302186250686646},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.39181628823280334},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.1898331642150879},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.18533474206924438},{"id":"https://openalex.org/C188817802","wikidata":"https://www.wikidata.org/wiki/Q13426855","display_name":"Physical design","level":3,"score":0.17401790618896484},{"id":"https://openalex.org/C31258907","wikidata":"https://www.wikidata.org/wiki/Q1301371","display_name":"Computer network","level":1,"score":0.1639707088470459},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.1566089689731598},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.09258297085762024},{"id":"https://openalex.org/C190560348","wikidata":"https://www.wikidata.org/wiki/Q3245116","display_name":"Circuit design","level":2,"score":0.07564595341682434},{"id":"https://openalex.org/C147789679","wikidata":"https://www.wikidata.org/wiki/Q11372","display_name":"Physical chemistry","level":1,"score":0.0},{"id":"https://openalex.org/C2524010","wikidata":"https://www.wikidata.org/wiki/Q8087","display_name":"Geometry","level":1,"score":0.0},{"id":"https://openalex.org/C154945302","wikidata":"https://www.wikidata.org/wiki/Q11660","display_name":"Artificial intelligence","level":1,"score":0.0},{"id":"https://openalex.org/C17525397","wikidata":"https://www.wikidata.org/wiki/Q176140","display_name":"Electrode","level":2,"score":0.0},{"id":"https://openalex.org/C185592680","wikidata":"https://www.wikidata.org/wiki/Q2329","display_name":"Chemistry","level":0,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1145/1514932.1514964","is_oa":false,"landing_page_url":"https://doi.org/10.1145/1514932.1514964","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 2009 international symposium on Physical design","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":21,"referenced_works":["https://openalex.org/W272982077","https://openalex.org/W1507707340","https://openalex.org/W1552851923","https://openalex.org/W1572342435","https://openalex.org/W1981555216","https://openalex.org/W1985843314","https://openalex.org/W2002242863","https://openalex.org/W2002982872","https://openalex.org/W2011039300","https://openalex.org/W2023981464","https://openalex.org/W2105750636","https://openalex.org/W2127118736","https://openalex.org/W2128335981","https://openalex.org/W2131239505","https://openalex.org/W2133916137","https://openalex.org/W2136964362","https://openalex.org/W2138817962","https://openalex.org/W2149417654","https://openalex.org/W2155911206","https://openalex.org/W2156857157","https://openalex.org/W2171134634"],"related_works":["https://openalex.org/W1987487129","https://openalex.org/W2164654367","https://openalex.org/W2150456555","https://openalex.org/W2185927297","https://openalex.org/W2153380648","https://openalex.org/W4296978184","https://openalex.org/W2098851424","https://openalex.org/W2951709973","https://openalex.org/W4237664122","https://openalex.org/W2123980833"],"abstract_inverted_index":{"In":[0],"modern":[1],"microprocessors,":[2],"clocks":[3],"are":[4,44],"usually":[5],"distributed":[6],"employing":[7,24],"a":[8,101,135,182,210],"hybrid":[9],"network,":[10],"grid":[11,34,48],"followed":[12],"by":[13,52,191],"buffered":[14,26,42],"trees,":[15],"to":[16,46,75,91,100,134,151,204],"restrict":[17],"the":[18,29,32,36,47,54,57,80,83,95,109,126,129,138,143,147,155,160,164,175,189,194],"skew.":[19],"This":[20,98],"is":[21,157,166,202],"typically":[22],"done":[23],"(gated)":[25],"trees":[27,43],"inside":[28],"blocks,":[30],"while":[31],"global":[33],"overlay":[35],"entire":[37],"die":[38],"area.":[39],"The":[40,60,200],"block-level":[41,84],"connected":[45],"at":[49,79],"specific":[50],"locations,":[51],"routing":[53,61,111,176],"wires":[55,88,114],"along":[56],"predetermined":[58],"tracks.":[59],"of":[62,82,103,128,179],"these":[63,87],"clock":[64,96,207],"wires,":[65],"which":[66],"consume":[67],"noticeable":[68],"power,":[69],"have":[70],"distance":[71,121,145],"and":[72,118,122,146],"capacitance":[73,104,123,149],"constraints":[74],"avoid":[76],"poor":[77],"slopes":[78],"inputs":[81],"buffers.":[85],"Moreover,":[86],"also":[89],"contribute":[90],"significant":[92],"load":[93],"on":[94,137,154],"grid.":[97],"leads":[99],"problem":[102,165],"or":[105],"wirelength":[106,190],"minimization":[107],"during":[108],"multi-terminal":[110],"such":[112],"that":[113,173],"use":[115],"pre-specified":[116],"tracks":[117],"routes":[119],"obey":[120],"constraints,":[124],"i.e.,":[125],"length":[127],"route":[130,156],"from":[131],"any":[132],"receiver":[133],"connection":[136],"grid-wire":[139],"has":[140],"less":[141,158],"than":[142,159],"specified":[144],"overall":[148],"due":[150],"all":[152],"receivers":[153],"given":[161],"limit.":[162],"Since":[163],"intractable,":[167],"we":[168],"present":[169],"an":[170],"efficient":[171],"algorithm":[172,201],"completes":[174],"connecting":[177],"1000s":[178],"terminals":[180],"over":[181,193],"few":[183],"$mm^2$":[184],"area":[185],"in":[186,209],"seconds,":[187],"improving":[188],"17%":[192],"commonly":[195],"used":[196],"nearest":[197],"source":[198],"heuristic.":[199],"employed":[203],"perform":[205],"post-grid":[206],"distribution":[208],"45":[211],"nm":[212],"technology":[213],"microprocessor.":[214]},"counts_by_year":[{"year":2017,"cited_by_count":1},{"year":2014,"cited_by_count":2},{"year":2013,"cited_by_count":1},{"year":2012,"cited_by_count":3}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}