{"id":"https://openalex.org/W1994883694","doi":"https://doi.org/10.1145/1514932.1514955","title":"Physical optimization for FPGAs using post-placement topology rewriting","display_name":"Physical optimization for FPGAs using post-placement topology rewriting","publication_year":2009,"publication_date":"2009-03-29","ids":{"openalex":"https://openalex.org/W1994883694","doi":"https://doi.org/10.1145/1514932.1514955","mag":"1994883694"},"language":"en","primary_location":{"id":"doi:10.1145/1514932.1514955","is_oa":false,"landing_page_url":"https://doi.org/10.1145/1514932.1514955","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 2009 international symposium on Physical design","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5070951209","display_name":"Val Pevzner","orcid":null},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"Val Pevzner","raw_affiliation_strings":["Actel Corporation, Mountain View, CA, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Actel Corporation, Mountain View, CA, USA","institution_ids":[]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5007026340","display_name":"Andrew Kennings","orcid":null},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"Andrew Kennings","raw_affiliation_strings":["Actel Corporation, Waterloo, ON, Canada"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Actel Corporation, Waterloo, ON, Canada","institution_ids":[]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5025559864","display_name":"Andy Fox","orcid":null},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"Andy Fox","raw_affiliation_strings":["Actel Corporation, Mountain View, CA, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Actel Corporation, Mountain View, CA, USA","institution_ids":[]}]}],"institutions":[],"countries_distinct_count":0,"institutions_distinct_count":3,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":0.8043,"has_fulltext":false,"cited_by_count":4,"citation_normalized_percentile":{"value":0.72464042,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":90,"max":94},"biblio":{"volume":null,"issue":null,"first_page":"91","last_page":"98"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9993000030517578,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.7686805725097656},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.6755806803703308},{"id":"https://openalex.org/keywords/rewriting","display_name":"Rewriting","score":0.6615753173828125},{"id":"https://openalex.org/keywords/decomposition","display_name":"Decomposition","score":0.5562220811843872},{"id":"https://openalex.org/keywords/logic-synthesis","display_name":"Logic synthesis","score":0.48948442935943604},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.47484496235847473},{"id":"https://openalex.org/keywords/topology","display_name":"Topology (electrical circuits)","score":0.4379497766494751},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.4084915220737457},{"id":"https://openalex.org/keywords/logic-gate","display_name":"Logic gate","score":0.3725125789642334},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.2871232032775879},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.21937361359596252},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.15610641241073608},{"id":"https://openalex.org/keywords/programming-language","display_name":"Programming language","score":0.15284347534179688},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.0728096067905426}],"concepts":[{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.7686805725097656},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6755806803703308},{"id":"https://openalex.org/C154690210","wikidata":"https://www.wikidata.org/wiki/Q1668499","display_name":"Rewriting","level":2,"score":0.6615753173828125},{"id":"https://openalex.org/C124681953","wikidata":"https://www.wikidata.org/wiki/Q339062","display_name":"Decomposition","level":2,"score":0.5562220811843872},{"id":"https://openalex.org/C157922185","wikidata":"https://www.wikidata.org/wiki/Q173198","display_name":"Logic synthesis","level":3,"score":0.48948442935943604},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.47484496235847473},{"id":"https://openalex.org/C184720557","wikidata":"https://www.wikidata.org/wiki/Q7825049","display_name":"Topology (electrical circuits)","level":2,"score":0.4379497766494751},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.4084915220737457},{"id":"https://openalex.org/C131017901","wikidata":"https://www.wikidata.org/wiki/Q170451","display_name":"Logic gate","level":2,"score":0.3725125789642334},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.2871232032775879},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.21937361359596252},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.15610641241073608},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.15284347534179688},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.0728096067905426},{"id":"https://openalex.org/C18903297","wikidata":"https://www.wikidata.org/wiki/Q7150","display_name":"Ecology","level":1,"score":0.0},{"id":"https://openalex.org/C86803240","wikidata":"https://www.wikidata.org/wiki/Q420","display_name":"Biology","level":0,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1145/1514932.1514955","is_oa":false,"landing_page_url":"https://doi.org/10.1145/1514932.1514955","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 2009 international symposium on Physical design","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":21,"referenced_works":["https://openalex.org/W1905608265","https://openalex.org/W1985457698","https://openalex.org/W2000478871","https://openalex.org/W2035561773","https://openalex.org/W2052067881","https://openalex.org/W2096185144","https://openalex.org/W2099134576","https://openalex.org/W2100465945","https://openalex.org/W2100955320","https://openalex.org/W2105715355","https://openalex.org/W2108508582","https://openalex.org/W2114364095","https://openalex.org/W2129388028","https://openalex.org/W2133743520","https://openalex.org/W2134060873","https://openalex.org/W2150787480","https://openalex.org/W2153585893","https://openalex.org/W2159111323","https://openalex.org/W2159221249","https://openalex.org/W2163492764","https://openalex.org/W2165081508"],"related_works":["https://openalex.org/W1967938402","https://openalex.org/W2386041993","https://openalex.org/W1608572506","https://openalex.org/W2098419840","https://openalex.org/W1966764473","https://openalex.org/W2130565894","https://openalex.org/W1944377106","https://openalex.org/W2901661247","https://openalex.org/W2789349722","https://openalex.org/W4312497944"],"abstract_inverted_index":{"Due":[0],"to":[1,22],"poor":[2],"correlations":[3],"between":[4],"pre-":[5],"and":[6],"post-placement":[7,11],"timing":[8],"analysis,":[9],"many":[10],"optimization":[12],"strategies":[13],"have":[14],"been":[15],"proposed":[16],"for":[17],"the":[18],"FPGA":[19],"CAD":[20],"flow":[21],"improve":[23],"circuit":[24],"performance.":[25],"Typically,":[26],"these":[27],"methods":[28,35],"depend":[29],"on":[30],"logic":[31],"duplication":[32],"or":[33],"decomposition":[34],"combine":[36],"together":[37],"with":[38],"incremental":[39],"placement.":[40]},"counts_by_year":[{"year":2019,"cited_by_count":1}],"updated_date":"2026-06-11T09:08:48.828518","created_date":"2025-10-10T00:00:00"}