{"id":"https://openalex.org/W2171626895","doi":"https://doi.org/10.1145/1508128.1508203","title":"High-performance, cost-effective heterogeneous 3D FPGA architectures","display_name":"High-performance, cost-effective heterogeneous 3D FPGA architectures","publication_year":2009,"publication_date":"2009-02-22","ids":{"openalex":"https://openalex.org/W2171626895","doi":"https://doi.org/10.1145/1508128.1508203","mag":"2171626895"},"language":"en","primary_location":{"id":"doi:10.1145/1508128.1508203","is_oa":false,"landing_page_url":"https://doi.org/10.1145/1508128.1508203","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the ACM/SIGDA international symposium on Field programmable gate arrays","raw_type":"proceedings-article"},"type":"conference-paper","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5086195866","display_name":"Roto Le","orcid":null},"institutions":[{"id":"https://openalex.org/I27804330","display_name":"Brown University","ror":"https://ror.org/05gq02987","country_code":"US","type":"education","lineage":["https://openalex.org/I27804330"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Roto Le","raw_affiliation_strings":["Brown University, Providence, RI, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Brown University, Providence, RI, USA","institution_ids":["https://openalex.org/I27804330"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5015719218","display_name":"Sherief Reda","orcid":"https://orcid.org/0000-0001-8232-4516"},"institutions":[{"id":"https://openalex.org/I27804330","display_name":"Brown University","ror":"https://ror.org/05gq02987","country_code":"US","type":"education","lineage":["https://openalex.org/I27804330"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Sherief Reda","raw_affiliation_strings":["Brown University, Providence, RI, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Brown University, Providence, RI, USA","institution_ids":["https://openalex.org/I27804330"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5019716170","display_name":"Iris Bahar","orcid":null},"institutions":[{"id":"https://openalex.org/I27804330","display_name":"Brown University","ror":"https://ror.org/05gq02987","country_code":"US","type":"education","lineage":["https://openalex.org/I27804330"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Iris Bahar","raw_affiliation_strings":["Brown University, Providence, RI, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Brown University, Providence, RI, USA","institution_ids":["https://openalex.org/I27804330"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":1,"corresponding_author_ids":[],"corresponding_institution_ids":["https://openalex.org/I27804330"],"apc_list":null,"apc_paid":null,"fwci":1.4563,"has_fulltext":false,"cited_by_count":9,"citation_normalized_percentile":{"value":0.82403905,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":94,"max":96},"biblio":{"volume":null,"issue":null,"first_page":"286","last_page":"286"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11527","display_name":"3D IC and TSV technologies","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11527","display_name":"3D IC and TSV technologies","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.9991999864578247,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9991999864578247,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.8574670553207397},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.6391137838363647},{"id":"https://openalex.org/keywords/interconnection","display_name":"Interconnection","score":0.6242042779922485},{"id":"https://openalex.org/keywords/die","display_name":"Die (integrated circuit)","score":0.6056364178657532},{"id":"https://openalex.org/keywords/reduction","display_name":"Reduction (mathematics)","score":0.4943079948425293},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.47308236360549927},{"id":"https://openalex.org/keywords/cost-reduction","display_name":"Cost reduction","score":0.4251159429550171},{"id":"https://openalex.org/keywords/telecommunications","display_name":"Telecommunications","score":0.07804164290428162}],"concepts":[{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.8574670553207397},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6391137838363647},{"id":"https://openalex.org/C123745756","wikidata":"https://www.wikidata.org/wiki/Q1665949","display_name":"Interconnection","level":2,"score":0.6242042779922485},{"id":"https://openalex.org/C111106434","wikidata":"https://www.wikidata.org/wiki/Q1072430","display_name":"Die (integrated circuit)","level":2,"score":0.6056364178657532},{"id":"https://openalex.org/C111335779","wikidata":"https://www.wikidata.org/wiki/Q3454686","display_name":"Reduction (mathematics)","level":2,"score":0.4943079948425293},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.47308236360549927},{"id":"https://openalex.org/C2778820799","wikidata":"https://www.wikidata.org/wiki/Q3454688","display_name":"Cost reduction","level":2,"score":0.4251159429550171},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.07804164290428162},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.0},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.0},{"id":"https://openalex.org/C187736073","wikidata":"https://www.wikidata.org/wiki/Q2920921","display_name":"Management","level":1,"score":0.0},{"id":"https://openalex.org/C2524010","wikidata":"https://www.wikidata.org/wiki/Q8087","display_name":"Geometry","level":1,"score":0.0},{"id":"https://openalex.org/C162324750","wikidata":"https://www.wikidata.org/wiki/Q8134","display_name":"Economics","level":0,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1145/1508128.1508203","is_oa":false,"landing_page_url":"https://doi.org/10.1145/1508128.1508203","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the ACM/SIGDA international symposium on Field programmable gate arrays","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"display_name":"Industry, innovation and infrastructure","score":0.6499999761581421,"id":"https://metadata.un.org/sdg/9"}],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":15,"referenced_works":["https://openalex.org/W1523051745","https://openalex.org/W1970296212","https://openalex.org/W2041266765","https://openalex.org/W2057027737","https://openalex.org/W2071003187","https://openalex.org/W2119916477","https://openalex.org/W2122065282","https://openalex.org/W2129785295","https://openalex.org/W2138438526","https://openalex.org/W2139243942","https://openalex.org/W2144149750","https://openalex.org/W2146185334","https://openalex.org/W2150073849","https://openalex.org/W2157890680","https://openalex.org/W2170034300"],"related_works":["https://openalex.org/W2042913821","https://openalex.org/W2372289614","https://openalex.org/W2629813803","https://openalex.org/W2041067810","https://openalex.org/W2250518232","https://openalex.org/W4384785625","https://openalex.org/W1979716082","https://openalex.org/W4242594920","https://openalex.org/W2812758604","https://openalex.org/W2087637582"],"abstract_inverted_index":{"In":[0],"this":[1],"paper,":[2],"we":[3,131,178],"propose":[4],"novel":[5,24,134],"architectural":[6],"and":[7,50,79,126,153],"design":[8,25,132],"techniques":[9],"for":[10],"three-dimensional":[11],"field-programmable":[12],"gate":[13],"arrays":[14],"(3D":[15],"FPGAs)":[16],"with":[17,138,194],"Through-Silicon":[18],"Vias":[19],"(TSVs).":[20],"We":[21,141],"develop":[22],"a":[23,38,133,174,195],"partitioning":[26,148],"methodology":[27],"that":[28,43,160,180],"maps":[29],"the":[30,44,51,57,77,81,90,104,144,155,162,171],"heterogeneous":[31],"computational":[32],"resources":[33,99],"of":[34,40,92,117,128,146,158,188,200],"an":[35,69,185],"FPGA":[36,52],"into":[37,102],"number":[39,157],"die":[41,46,59,115,151,159,167,192],"such":[42],"total":[45,58,114,166,191],"area":[47,60,94,106,116,125,152,168,193],"is":[48,54,68,86,111],"minimized":[49],"performance":[53,127],"maximized.":[55],"Minimizing":[56],"leads":[61],"to":[62,72,76,88,113,123],"direct":[63],"manufacturing":[64],"cost":[65],"savings":[66],"which":[67,110],"important":[70],"incentive":[71],"bring":[73],"3D":[74,97,118,129,135],"technology":[75],"fab":[78],"onto":[80],"market.":[82],"An":[83],"estimation":[84],"framework":[85],"developed":[87],"assess":[89],"impact":[91,145],"silicon":[93],"utilized":[95],"by":[96,108],"interconnect":[98,197],"while":[100,169],"taking":[101],"account":[103],"large":[105],"occupied":[107],"TSVs":[109],"crucial":[112],"FPGA.":[119],"And":[120],"in":[121,165,190],"order":[122],"improve":[124],"FPGA,":[130],"switch":[136],"box":[137],"bypass":[139],"TSVs.":[140],"also":[142],"analyze":[143],"different":[147],"strategies":[149],"on":[150],"find":[154],"optimal":[156],"gives":[161],"largest":[163],"reductions":[164],"maximizing":[170],"performance.":[172],"Using":[173],"well-developed":[175],"simulation":[176],"infrastructure,":[177],"show":[179],"our":[181],"methodologies":[182],"can":[183],"achieve":[184],"average":[186],"reduction":[187],"27.7%":[189],"reduced":[196],"path":[198],"delay":[199],"about":[201],"58%.":[202]},"counts_by_year":[{"year":2015,"cited_by_count":2},{"year":2014,"cited_by_count":2},{"year":2013,"cited_by_count":2},{"year":2012,"cited_by_count":2}],"updated_date":"2026-07-29T14:22:42.915294","created_date":"2025-10-10T00:00:00"}