{"id":"https://openalex.org/W1980653897","doi":"https://doi.org/10.1145/1508128.1508200","title":"A novel BIST approach for testing input/output buffers in FPGAs","display_name":"A novel BIST approach for testing input/output buffers in FPGAs","publication_year":2009,"publication_date":"2009-02-22","ids":{"openalex":"https://openalex.org/W1980653897","doi":"https://doi.org/10.1145/1508128.1508200","mag":"1980653897"},"language":"en","primary_location":{"id":"doi:10.1145/1508128.1508200","is_oa":false,"landing_page_url":"https://doi.org/10.1145/1508128.1508200","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the ACM/SIGDA international symposium on Field programmable gate arrays","raw_type":"proceedings-article"},"type":"conference-abstract","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":null,"display_name":"Chen Lei","orcid":null},"institutions":[{"id":"https://openalex.org/I4210089056","display_name":"Beijing Microelectronics Technology Institute","ror":"https://ror.org/007y7ej30","country_code":"CN","type":"other","lineage":["https://openalex.org/I4210089056"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Chen Lei","raw_affiliation_strings":["Beijing Microelectronics Technology Institution, Beijing, China"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Beijing Microelectronics Technology Institution, Beijing, China","institution_ids":["https://openalex.org/I4210089056"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5046394421","display_name":"Zhang Zhi Quan","orcid":null},"institutions":[{"id":"https://openalex.org/I4210089056","display_name":"Beijing Microelectronics Technology Institute","ror":"https://ror.org/007y7ej30","country_code":"CN","type":"other","lineage":["https://openalex.org/I4210089056"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Zhang Zhi Quan","raw_affiliation_strings":["Beijing Microelectronics Technology Institution, Beijing, China"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Beijing Microelectronics Technology Institution, Beijing, China","institution_ids":["https://openalex.org/I4210089056"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5075028712","display_name":"Wen Ping","orcid":null},"institutions":[{"id":"https://openalex.org/I4210089056","display_name":"Beijing Microelectronics Technology Institute","ror":"https://ror.org/007y7ej30","country_code":"CN","type":"other","lineage":["https://openalex.org/I4210089056"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Wen Zhi Ping","raw_affiliation_strings":["Beijing Microelectronics Technology Institution, Beijing, China"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Beijing Microelectronics Technology Institution, Beijing, China","institution_ids":["https://openalex.org/I4210089056"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":1,"corresponding_author_ids":[],"corresponding_institution_ids":["https://openalex.org/I4210089056"],"apc_list":null,"apc_paid":null,"fwci":null,"has_fulltext":false,"cited_by_count":0,"citation_normalized_percentile":null,"cited_by_percentile_year":null,"biblio":{"volume":null,"issue":null,"first_page":"285","last_page":"285"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T14117","display_name":"Integrated Circuits and Semiconductor Failure Analysis","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T12122","display_name":"Physical Unclonable Functions (PUFs) and Hardware Security","score":0.9991000294685364,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.902542769908905},{"id":"https://openalex.org/keywords/virtex","display_name":"Virtex","score":0.8568998575210571},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.6943433284759521},{"id":"https://openalex.org/keywords/routing","display_name":"Routing (electronic design automation)","score":0.6545954942703247},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.6306793689727783},{"id":"https://openalex.org/keywords/built-in-self-test","display_name":"Built-in self-test","score":0.6168023943901062},{"id":"https://openalex.org/keywords/reconfigurable-computing","display_name":"Reconfigurable computing","score":0.48002639412879944},{"id":"https://openalex.org/keywords/series","display_name":"Series (stratigraphy)","score":0.4618813693523407},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.4074181318283081},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.34120702743530273},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.33010879158973694}],"concepts":[{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.902542769908905},{"id":"https://openalex.org/C2777674469","wikidata":"https://www.wikidata.org/wiki/Q20741011","display_name":"Virtex","level":3,"score":0.8568998575210571},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6943433284759521},{"id":"https://openalex.org/C74172769","wikidata":"https://www.wikidata.org/wiki/Q1446839","display_name":"Routing (electronic design automation)","level":2,"score":0.6545954942703247},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.6306793689727783},{"id":"https://openalex.org/C2780980493","wikidata":"https://www.wikidata.org/wiki/Q181142","display_name":"Built-in self-test","level":2,"score":0.6168023943901062},{"id":"https://openalex.org/C142962650","wikidata":"https://www.wikidata.org/wiki/Q240838","display_name":"Reconfigurable computing","level":3,"score":0.48002639412879944},{"id":"https://openalex.org/C143724316","wikidata":"https://www.wikidata.org/wiki/Q312468","display_name":"Series (stratigraphy)","level":2,"score":0.4618813693523407},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.4074181318283081},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.34120702743530273},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.33010879158973694},{"id":"https://openalex.org/C86803240","wikidata":"https://www.wikidata.org/wiki/Q420","display_name":"Biology","level":0,"score":0.0},{"id":"https://openalex.org/C151730666","wikidata":"https://www.wikidata.org/wiki/Q7205","display_name":"Paleontology","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1145/1508128.1508200","is_oa":false,"landing_page_url":"https://doi.org/10.1145/1508128.1508200","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the ACM/SIGDA international symposium on Field programmable gate arrays","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"id":"https://metadata.un.org/sdg/9","display_name":"Industry, innovation and infrastructure","score":0.41999998688697815}],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":5,"referenced_works":["https://openalex.org/W1949652524","https://openalex.org/W2108142023","https://openalex.org/W2145557593","https://openalex.org/W2146415000","https://openalex.org/W2161901910"],"related_works":["https://openalex.org/W2544043553","https://openalex.org/W2546284597","https://openalex.org/W2348562861","https://openalex.org/W2540393334","https://openalex.org/W3146360095","https://openalex.org/W1983570530","https://openalex.org/W2390042878","https://openalex.org/W2062932566","https://openalex.org/W2271847574","https://openalex.org/W2746234147"],"abstract_inverted_index":{"A":[0],"novel":[1],"Built-In":[2],"Self-Test":[3],"(BIST)":[4],"approach":[5,28],"to":[6,69],"test":[7,73],"the":[8,75],"configurable":[9],"Input/Output":[10],"buffers":[11,77],"in":[12,23,44,78],"Xilinx":[13,58],"Virtex":[14,59,79],"series":[15,60,80],"FPGAs":[16],"using":[17],"Hard":[18],"Macro":[19],"has":[20,51],"been":[21,52],"proposed":[22,27,48],"this":[24],"paper.":[25],"The":[26,47],"can":[29],"completely":[30,70],"detects":[31],"single":[32],"and":[33,55],"multiple":[34],"stuck-at":[35],"gate-level":[36],"faults":[37],"as":[38,40],"well":[39],"associated":[41],"routing":[42],"resources":[43],"I/O":[45,76],"buffers.":[46],"BIST":[49],"architecture":[50],"successfully":[53],"implemented":[54],"verified":[56],"on":[57],"FPGA.":[61,81],"Only":[62],"total":[63],"of":[64,74],"eight":[65],"configurations":[66],"are":[67],"required":[68],"built-in":[71],"self":[72]},"counts_by_year":[],"updated_date":"2026-07-14T23:27:15.235271","created_date":"2025-10-10T00:00:00"}