{"id":"https://openalex.org/W2063723758","doi":"https://doi.org/10.1145/1508128.1508195","title":"Streaming implementation of a sequential decompression algorithm on an FPGA","display_name":"Streaming implementation of a sequential decompression algorithm on an FPGA","publication_year":2009,"publication_date":"2009-02-22","ids":{"openalex":"https://openalex.org/W2063723758","doi":"https://doi.org/10.1145/1508128.1508195","mag":"2063723758"},"language":"en","primary_location":{"id":"doi:10.1145/1508128.1508195","is_oa":false,"landing_page_url":"https://doi.org/10.1145/1508128.1508195","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the ACM/SIGDA international symposium on Field programmable gate arrays","raw_type":"proceedings-article"},"type":"conference-paper","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5040169078","display_name":"Gaurav Mittal","orcid":"https://orcid.org/0000-0001-8292-9646"},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"Gaurav Mittal","raw_affiliation_strings":["Binachip, Inc, Chicago, IL, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Binachip, Inc, Chicago, IL, USA","institution_ids":[]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5088154827","display_name":"David Zaretsky","orcid":null},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"David C. Zaretsky","raw_affiliation_strings":["Binachip, Inc, Chicago, IL, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Binachip, Inc, Chicago, IL, USA","institution_ids":[]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5100803950","display_name":"Prithviraj Banerjee","orcid":null},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"Prithviraj Banerjee","raw_affiliation_strings":["Binachip, Inc, Chicago, IL, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Binachip, Inc, Chicago, IL, USA","institution_ids":[]}]}],"institutions":[],"countries_distinct_count":0,"institutions_distinct_count":0,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":0.3658,"has_fulltext":false,"cited_by_count":2,"citation_normalized_percentile":{"value":0.50981932,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":null,"issue":null,"first_page":"283","last_page":"283"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9994000196456909,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10933","display_name":"Real-Time Systems Scheduling","score":0.9979000091552734,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.8387002944946289},{"id":"https://openalex.org/keywords/pentium","display_name":"Pentium","score":0.7335258722305298},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.6036404967308044},{"id":"https://openalex.org/keywords/vhdl","display_name":"VHDL","score":0.5675981640815735},{"id":"https://openalex.org/keywords/exploit","display_name":"Exploit","score":0.5577069520950317},{"id":"https://openalex.org/keywords/software","display_name":"Software","score":0.5490619540214539},{"id":"https://openalex.org/keywords/compiler","display_name":"Compiler","score":0.5291503071784973},{"id":"https://openalex.org/keywords/speedup","display_name":"Speedup","score":0.5132565498352051},{"id":"https://openalex.org/keywords/workstation","display_name":"Workstation","score":0.5037395358085632},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.38956016302108765},{"id":"https://openalex.org/keywords/operating-system","display_name":"Operating system","score":0.35821011662483215},{"id":"https://openalex.org/keywords/computer-security","display_name":"Computer security","score":0.10400474071502686}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.8387002944946289},{"id":"https://openalex.org/C46268123","wikidata":"https://www.wikidata.org/wiki/Q214314","display_name":"Pentium","level":2,"score":0.7335258722305298},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.6036404967308044},{"id":"https://openalex.org/C36941000","wikidata":"https://www.wikidata.org/wiki/Q209455","display_name":"VHDL","level":3,"score":0.5675981640815735},{"id":"https://openalex.org/C165696696","wikidata":"https://www.wikidata.org/wiki/Q11287","display_name":"Exploit","level":2,"score":0.5577069520950317},{"id":"https://openalex.org/C2777904410","wikidata":"https://www.wikidata.org/wiki/Q7397","display_name":"Software","level":2,"score":0.5490619540214539},{"id":"https://openalex.org/C169590947","wikidata":"https://www.wikidata.org/wiki/Q47506","display_name":"Compiler","level":2,"score":0.5291503071784973},{"id":"https://openalex.org/C68339613","wikidata":"https://www.wikidata.org/wiki/Q1549489","display_name":"Speedup","level":2,"score":0.5132565498352051},{"id":"https://openalex.org/C67953723","wikidata":"https://www.wikidata.org/wiki/Q192525","display_name":"Workstation","level":2,"score":0.5037395358085632},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.38956016302108765},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.35821011662483215},{"id":"https://openalex.org/C38652104","wikidata":"https://www.wikidata.org/wiki/Q3510521","display_name":"Computer security","level":1,"score":0.10400474071502686}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1145/1508128.1508195","is_oa":false,"landing_page_url":"https://doi.org/10.1145/1508128.1508195","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the ACM/SIGDA international symposium on Field programmable gate arrays","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"id":"https://metadata.un.org/sdg/17","display_name":"Partnerships for the goals","score":0.49000000953674316}],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":12,"referenced_works":["https://openalex.org/W2000351691","https://openalex.org/W2080285119","https://openalex.org/W2087897516","https://openalex.org/W2112432448","https://openalex.org/W2112482891","https://openalex.org/W2132244976","https://openalex.org/W2162693073","https://openalex.org/W2244090709","https://openalex.org/W3023634467","https://openalex.org/W4285719527","https://openalex.org/W6676285976","https://openalex.org/W6682962067"],"related_works":["https://openalex.org/W1597195064","https://openalex.org/W2058965144","https://openalex.org/W2164382479","https://openalex.org/W2146343568","https://openalex.org/W98480971","https://openalex.org/W2150291671","https://openalex.org/W2013643406","https://openalex.org/W1534644390","https://openalex.org/W2778498407","https://openalex.org/W2388434383"],"abstract_inverted_index":{"This":[0],"paper":[1],"describes":[2],"an":[3],"FPGA":[4,127],"based":[5],"implementation":[6,137],"of":[7,56,75,90,110,153],"a":[8,27,48,73,98,123,129,135,140],"real":[9],"time":[10],"compression":[11],"algorithm":[12],"used":[13],"in":[14,77,94,103,132],"transactions":[15],"between":[16],"financial":[17,36,49,63],"institutions":[18],"such":[19,38],"as":[20,39,151],"exchanges":[21],"and":[22,42,86],"trading":[23],"houses.":[24],"FIX":[25],"is":[26,72],"protocol":[28],"that":[29],"has":[30],"gained":[31],"widespread":[32],"popularity":[33],"for":[34],"exchanging":[35],"information":[37],"stock":[40],"prices":[41],"purchases":[43],"over":[44,134],"the":[45,54,78,91,108],"Internet.":[46],"If":[47],"trader":[50],"can":[51,60],"speed":[52],"up":[53],"processing":[55,101],"these":[57],"protocols,":[58],"he":[59],"make":[61],"significant":[62],"profits":[64],"by":[65],"buying":[66],"or":[67],"selling":[68],"stocks":[69],"when":[70],"there":[71],"lot":[74],"variability":[76],"share":[79],"prices.":[80],"Our":[81],"methodology":[82],"tries":[83],"to":[84,96,112,157,162],"recognize":[85],"exploit":[87],"streaming":[88,163],"characteristics":[89],"software":[92,136,160],"design":[93],"order":[95],"implement":[97],"pipelined":[99],"parallel":[100],"system":[102,120],"reconfigurable":[104],"hardware.":[105],"It":[106],"introduces":[107],"concept":[109],"caches":[111],"keep":[113],"stream":[114],"pipelines":[115],"filled":[116],"more":[117],"often.":[118],"The":[119],"implemented":[121],"on":[122,139],"Xilinx":[124],"Virtex5":[125],"LX110T":[126],"shows":[128],"17x":[130],"speedup":[131],"throughput":[133],"running":[138],"dual":[141],"core":[142],"Intel":[143],"Pentium":[144],"workstation.":[145],"These":[146],"techniques":[147],"are":[148],"being":[149],"developed":[150],"part":[152],"commercial":[154],"compiler":[155],"project":[156],"automatically":[158],"translate":[159],"binaries":[161],"RTL":[164],"VHDL":[165],"systems.":[166]},"counts_by_year":[],"updated_date":"2026-07-29T14:22:42.915294","created_date":"2025-10-10T00:00:00"}
