{"id":"https://openalex.org/W2030073746","doi":"https://doi.org/10.1145/1508128.1508189","title":"Performance and power of cache-based reconfigurable computing","display_name":"Performance and power of cache-based reconfigurable computing","publication_year":2009,"publication_date":"2009-02-22","ids":{"openalex":"https://openalex.org/W2030073746","doi":"https://doi.org/10.1145/1508128.1508189","mag":"2030073746"},"language":"en","primary_location":{"id":"doi:10.1145/1508128.1508189","is_oa":false,"landing_page_url":"https://doi.org/10.1145/1508128.1508189","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the ACM/SIGDA international symposium on Field programmable gate arrays","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5024883549","display_name":"Andrew Putnam","orcid":"https://orcid.org/0000-0001-5241-5695"},"institutions":[{"id":"https://openalex.org/I201448701","display_name":"University of Washington","ror":"https://ror.org/00cvxb145","country_code":"US","type":"education","lineage":["https://openalex.org/I201448701"]}],"countries":["US"],"is_corresponding":true,"raw_author_name":"Andrew Putnam","raw_affiliation_strings":["University of Washington, Seattle, WA, USA"],"affiliations":[{"raw_affiliation_string":"University of Washington, Seattle, WA, USA","institution_ids":["https://openalex.org/I201448701"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5051475447","display_name":"Susan J. Eggers","orcid":null},"institutions":[{"id":"https://openalex.org/I201448701","display_name":"University of Washington","ror":"https://ror.org/00cvxb145","country_code":"US","type":"education","lineage":["https://openalex.org/I201448701"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Susan Eggers","raw_affiliation_strings":["University of Washington, Seattle, WA, USA"],"affiliations":[{"raw_affiliation_string":"University of Washington, Seattle, WA, USA","institution_ids":["https://openalex.org/I201448701"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5036964031","display_name":"Dave Bennett","orcid":null},"institutions":[{"id":"https://openalex.org/I32923980","display_name":"Xilinx (United States)","ror":"https://ror.org/01rb7bk56","country_code":"US","type":"company","lineage":["https://openalex.org/I32923980"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Dave Bennett","raw_affiliation_strings":["Xilinx, Longmont, CO, USA"],"affiliations":[{"raw_affiliation_string":"Xilinx, Longmont, CO, USA","institution_ids":["https://openalex.org/I32923980"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5070616806","display_name":"Eric Dellinger","orcid":null},"institutions":[{"id":"https://openalex.org/I32923980","display_name":"Xilinx (United States)","ror":"https://ror.org/01rb7bk56","country_code":"US","type":"company","lineage":["https://openalex.org/I32923980"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Eric Dellinger","raw_affiliation_strings":["Xilinx, Longmont, CO, USA"],"affiliations":[{"raw_affiliation_string":"Xilinx, Longmont, CO, USA","institution_ids":["https://openalex.org/I32923980"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5061886781","display_name":"Jeff Mason","orcid":null},"institutions":[{"id":"https://openalex.org/I32923980","display_name":"Xilinx (United States)","ror":"https://ror.org/01rb7bk56","country_code":"US","type":"company","lineage":["https://openalex.org/I32923980"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Jeff Mason","raw_affiliation_strings":["Xilinx, Longmont, CO, USA"],"affiliations":[{"raw_affiliation_string":"Xilinx, Longmont, CO, USA","institution_ids":["https://openalex.org/I32923980"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5041588521","display_name":"Henry Styles","orcid":null},"institutions":[{"id":"https://openalex.org/I32923980","display_name":"Xilinx (United States)","ror":"https://ror.org/01rb7bk56","country_code":"US","type":"company","lineage":["https://openalex.org/I32923980"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Henry Styles","raw_affiliation_strings":["Xilinx, San Jose, CA, USA"],"affiliations":[{"raw_affiliation_string":"Xilinx, San Jose, CA, USA","institution_ids":["https://openalex.org/I32923980"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5000693480","display_name":"Prasanna Sundararajan","orcid":null},"institutions":[{"id":"https://openalex.org/I32923980","display_name":"Xilinx (United States)","ror":"https://ror.org/01rb7bk56","country_code":"US","type":"company","lineage":["https://openalex.org/I32923980"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Prasanna Sundararajan","raw_affiliation_strings":["Xilinx, San Jose, CA, USA"],"affiliations":[{"raw_affiliation_string":"Xilinx, San Jose, CA, USA","institution_ids":["https://openalex.org/I32923980"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5030738948","display_name":"Ralph Wittig","orcid":null},"institutions":[{"id":"https://openalex.org/I32923980","display_name":"Xilinx (United States)","ror":"https://ror.org/01rb7bk56","country_code":"US","type":"company","lineage":["https://openalex.org/I32923980"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Ralph Wittig","raw_affiliation_strings":["Xilinx, San Jose, CA, USA"],"affiliations":[{"raw_affiliation_string":"Xilinx, San Jose, CA, USA","institution_ids":["https://openalex.org/I32923980"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":8,"corresponding_author_ids":["https://openalex.org/A5024883549"],"corresponding_institution_ids":["https://openalex.org/I201448701"],"apc_list":null,"apc_paid":null,"fwci":1.21994175,"has_fulltext":false,"cited_by_count":6,"citation_normalized_percentile":{"value":0.87136681,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":98},"biblio":{"volume":null,"issue":null,"first_page":"281","last_page":"281"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9994000196456909,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.9958000183105469,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.8335718512535095},{"id":"https://openalex.org/keywords/cache","display_name":"Cache","score":0.7607356905937195},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.6731353998184204},{"id":"https://openalex.org/keywords/compiler","display_name":"Compiler","score":0.6138676404953003},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.4544830322265625},{"id":"https://openalex.org/keywords/cpu-cache","display_name":"CPU cache","score":0.4454456567764282},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.3807418644428253},{"id":"https://openalex.org/keywords/operating-system","display_name":"Operating system","score":0.2666788697242737}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.8335718512535095},{"id":"https://openalex.org/C115537543","wikidata":"https://www.wikidata.org/wiki/Q165596","display_name":"Cache","level":2,"score":0.7607356905937195},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.6731353998184204},{"id":"https://openalex.org/C169590947","wikidata":"https://www.wikidata.org/wiki/Q47506","display_name":"Compiler","level":2,"score":0.6138676404953003},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.4544830322265625},{"id":"https://openalex.org/C189783530","wikidata":"https://www.wikidata.org/wiki/Q352090","display_name":"CPU cache","level":3,"score":0.4454456567764282},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.3807418644428253},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.2666788697242737}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1145/1508128.1508189","is_oa":false,"landing_page_url":"https://doi.org/10.1145/1508128.1508189","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the ACM/SIGDA international symposium on Field programmable gate arrays","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"score":0.7300000190734863,"display_name":"Affordable and clean energy","id":"https://metadata.un.org/sdg/7"}],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":0,"referenced_works":[],"related_works":["https://openalex.org/W2167303720","https://openalex.org/W2133682266","https://openalex.org/W2497617944","https://openalex.org/W1563139915","https://openalex.org/W2109715593","https://openalex.org/W2061075966","https://openalex.org/W3147501184","https://openalex.org/W2268996566","https://openalex.org/W4256652509","https://openalex.org/W2140219379"],"abstract_inverted_index":{"CHiMPS":[0,14,83],"is":[1,128,139],"a":[2,28,53,98,110,143],"C-based":[3],"compiler":[4,84],"for":[5,67],"high-performance":[6],"computing":[7,12],"(HPC)":[8],"on":[9,43,97,106,129],"heterogeneous":[10],"CPU-FPGA":[11],"platforms.":[13],"efficiently":[15],"supports":[16],"random":[17],"accesses":[18],"to":[19,33],"main":[20],"memory":[21,25,60,69],"through":[22],"the":[23,68,77,82,91,94,120],"many-cache":[24,87],"model,":[26],"enabling":[27],"broader":[29],"range":[30],"of":[31,36,45,59,81,93,119,146],"applications":[32],"take":[34],"advantage":[35],"FPGA-based":[37],"acceleration.":[38],"Many-cache":[39],"creates":[40],"multiple":[41],"caches":[42],"top":[44],"an":[46,62],"FGPA's":[47],"small,":[48],"independent":[49],"memories,":[50],"each":[51,65],"targeting":[52],"particular":[54],"data":[55],"structure":[56],"or":[57],"region":[58],"in":[61],"application":[63],"and":[64,79,89,133],"customized":[66],"operations":[70],"that":[71,85,127,138],"access":[72],"it.":[73],"This":[74],"poster":[75],"presents":[76,90],"analyses":[78],"optimizations":[80],"construct":[86],"caches,":[88],"details":[92],"cache":[95],"parameters":[96],"Xilinx":[99],"Virtex-5":[100],"LX110T":[101],"FPGA.":[102],"Detailed":[103],"simulation":[104],"results":[105],"HPC":[107],"kernels":[108],"demonstrate":[109],"7.8x":[111],"(geometric":[112],"mean)":[113],"performance":[114,135],"boost":[115],"over":[116],"CPU-only":[117],"execution":[118],"same":[121],"source":[122],"code,":[123],"FPGA":[124],"power":[125],"usage":[126],"average":[130],"4.1x":[131],"less,":[132],"consequently":[134],"per":[136],"watt":[137],"also":[140],"greater,":[141],"by":[142],"geometric":[144],"mean":[145],"21.3x.":[147]},"counts_by_year":[{"year":2013,"cited_by_count":1},{"year":2012,"cited_by_count":5}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}