{"id":"https://openalex.org/W2033901873","doi":"https://doi.org/10.1145/1508128.1508186","title":"Parallel placement for FPGAs revisited","display_name":"Parallel placement for FPGAs revisited","publication_year":2009,"publication_date":"2009-02-22","ids":{"openalex":"https://openalex.org/W2033901873","doi":"https://doi.org/10.1145/1508128.1508186","mag":"2033901873"},"language":"en","primary_location":{"id":"doi:10.1145/1508128.1508186","is_oa":false,"landing_page_url":"https://doi.org/10.1145/1508128.1508186","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the ACM/SIGDA international symposium on Field programmable gate arrays","raw_type":"proceedings-article"},"type":"conference-abstract","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5086561910","display_name":"Cristinel Ababei","orcid":"https://orcid.org/0000-0002-7609-5304"},"institutions":[{"id":"https://openalex.org/I57328836","display_name":"North Dakota State University","ror":"https://ror.org/05h1bnb22","country_code":"US","type":"education","lineage":["https://openalex.org/I57328836"]}],"countries":["US"],"is_corresponding":true,"raw_author_name":"Cristinel Ababei","raw_affiliation_strings":["North Dakota State University, Fargo, ND, USA","North Dakota State University , Fargo, ND, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"North Dakota State University, Fargo, ND, USA","institution_ids":["https://openalex.org/I57328836"]},{"raw_affiliation_string":"North Dakota State University , Fargo, ND, USA","institution_ids":["https://openalex.org/I57328836"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":1,"corresponding_author_ids":["https://openalex.org/A5086561910"],"corresponding_institution_ids":["https://openalex.org/I57328836"],"apc_list":null,"apc_paid":null,"fwci":null,"has_fulltext":false,"cited_by_count":3,"citation_normalized_percentile":null,"cited_by_percentile_year":null,"biblio":{"volume":null,"issue":null,"first_page":"280","last_page":"280"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9997000098228455,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9997000098228455,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9990000128746033,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.9986000061035156,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.839707612991333},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.8109338879585266},{"id":"https://openalex.org/keywords/simulated-annealing","display_name":"Simulated annealing","score":0.685573935508728},{"id":"https://openalex.org/keywords/multithreading","display_name":"Multithreading","score":0.679726243019104},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.6567077040672302},{"id":"https://openalex.org/keywords/placement","display_name":"Placement","score":0.5411978363990784},{"id":"https://openalex.org/keywords/synchronization","display_name":"Synchronization (alternating current)","score":0.5166771411895752},{"id":"https://openalex.org/keywords/routing","display_name":"Routing (electronic design automation)","score":0.42383408546447754},{"id":"https://openalex.org/keywords/implementation","display_name":"Implementation","score":0.4110785722732544},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.3306615948677063},{"id":"https://openalex.org/keywords/thread","display_name":"Thread (computing)","score":0.30441492795944214},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.268310010433197},{"id":"https://openalex.org/keywords/circuit-design","display_name":"Circuit design","score":0.14135023951530457},{"id":"https://openalex.org/keywords/physical-design","display_name":"Physical design","score":0.07689344882965088}],"concepts":[{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.839707612991333},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.8109338879585266},{"id":"https://openalex.org/C126980161","wikidata":"https://www.wikidata.org/wiki/Q863783","display_name":"Simulated annealing","level":2,"score":0.685573935508728},{"id":"https://openalex.org/C201410400","wikidata":"https://www.wikidata.org/wiki/Q1064412","display_name":"Multithreading","level":3,"score":0.679726243019104},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.6567077040672302},{"id":"https://openalex.org/C117690923","wikidata":"https://www.wikidata.org/wiki/Q1484784","display_name":"Placement","level":4,"score":0.5411978363990784},{"id":"https://openalex.org/C2778562939","wikidata":"https://www.wikidata.org/wiki/Q1298791","display_name":"Synchronization (alternating current)","level":3,"score":0.5166771411895752},{"id":"https://openalex.org/C74172769","wikidata":"https://www.wikidata.org/wiki/Q1446839","display_name":"Routing (electronic design automation)","level":2,"score":0.42383408546447754},{"id":"https://openalex.org/C26713055","wikidata":"https://www.wikidata.org/wiki/Q245962","display_name":"Implementation","level":2,"score":0.4110785722732544},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.3306615948677063},{"id":"https://openalex.org/C138101251","wikidata":"https://www.wikidata.org/wiki/Q213092","display_name":"Thread (computing)","level":2,"score":0.30441492795944214},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.268310010433197},{"id":"https://openalex.org/C190560348","wikidata":"https://www.wikidata.org/wiki/Q3245116","display_name":"Circuit design","level":2,"score":0.14135023951530457},{"id":"https://openalex.org/C188817802","wikidata":"https://www.wikidata.org/wiki/Q13426855","display_name":"Physical design","level":3,"score":0.07689344882965088},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.0},{"id":"https://openalex.org/C127162648","wikidata":"https://www.wikidata.org/wiki/Q16858953","display_name":"Channel (broadcasting)","level":2,"score":0.0},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.0},{"id":"https://openalex.org/C31258907","wikidata":"https://www.wikidata.org/wiki/Q1301371","display_name":"Computer network","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1145/1508128.1508186","is_oa":false,"landing_page_url":"https://doi.org/10.1145/1508128.1508186","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the ACM/SIGDA international symposium on Field programmable gate arrays","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":0,"referenced_works":[],"related_works":["https://openalex.org/W2115561485","https://openalex.org/W1985089255","https://openalex.org/W2153202644","https://openalex.org/W2010970156","https://openalex.org/W2105895556","https://openalex.org/W2733115356","https://openalex.org/W2377593213","https://openalex.org/W4235861380","https://openalex.org/W2106625514","https://openalex.org/W3089467468"],"abstract_inverted_index":{"The":[0,22,64,89,122],"runtime":[1,51],"of":[2,20,40,60,120,131],"classic":[3],"sequential":[4],"placement":[5,28,67,73,118,125,140],"algorithms":[6],"for":[7,62],"FPGAs":[8],"continues":[9],"to":[10,25,31],"represent":[11],"a":[12,38,103],"serious":[13],"problem,":[14],"aggravated":[15],"by":[16,86],"the":[17,27,58,94,114,137],"continuous":[18],"increase":[19],"FPGAs.":[21],"traditional":[23],"way":[24],"parallelize":[26,113],"step":[29],"is":[30,69,99],"use":[32,59],"parallel":[33,85,124],"distributed":[34],"implementations":[35],"run":[36],"on":[37,147],"network":[39],"processors.":[41],"This":[42],"approach":[43],"can":[44],"suffer":[45],"from":[46,96],"significant":[47],"communication":[48],"and":[49,141,151],"synchronization":[50],"overheads.":[52],"To":[53],"address":[54],"that,":[55],"we":[56,112],"propose":[57],"multithreading":[61],"parallelization.":[63],"top":[65],"level":[66],"problem":[68],"decomposed":[70],"into":[71],"region-based":[72],"sub-problems":[74,80],"using":[75,93,102,133],"four-way":[76],"min-cut":[77],"partitioning.":[78],"These":[79],"are":[81],"then":[82],"processed":[83],"in":[84],"worker":[87],"threads.":[88],"final":[90],"solution,":[91],"constructed":[92],"results":[95],"all":[97],"sub-problems,":[98],"further":[100],"improved":[101],"fast":[104],"low-temperature":[105],"annealing":[106,116],"refinement":[107],"step.":[108],"Using":[109],"this":[110],"technique,":[111],"simulated":[115],"based":[117],"algorithm":[119,126],"VPR.":[121],"new":[123],"achieves":[127],"an":[128],"average":[129,148],"speed-up":[130],"2.5x":[132],"four":[134],"threads,":[135],"while":[136],"wirelength":[138],"after":[139,144],"circuit":[142],"delay":[143],"routing":[145],"increased":[146],"with":[149],"3.7%":[150],"2.15%":[152],"respectively.":[153]},"counts_by_year":[{"year":2020,"cited_by_count":1},{"year":2017,"cited_by_count":1}],"updated_date":"2026-07-14T23:27:15.235271","created_date":"2025-10-10T00:00:00"}