{"id":"https://openalex.org/W1964026059","doi":"https://doi.org/10.1145/1508128.1508174","title":"HW/SW methodologies for synchronization in FPGA multiprocessors","display_name":"HW/SW methodologies for synchronization in FPGA multiprocessors","publication_year":2009,"publication_date":"2009-02-22","ids":{"openalex":"https://openalex.org/W1964026059","doi":"https://doi.org/10.1145/1508128.1508174","mag":"1964026059"},"language":"en","primary_location":{"id":"doi:10.1145/1508128.1508174","is_oa":false,"landing_page_url":"https://doi.org/10.1145/1508128.1508174","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the ACM/SIGDA international symposium on Field programmable gate arrays","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5041853964","display_name":"Antonino Tumeo","orcid":"https://orcid.org/0000-0001-9452-120X"},"institutions":[{"id":"https://openalex.org/I93860229","display_name":"Politecnico di Milano","ror":"https://ror.org/01nffqt88","country_code":"IT","type":"education","lineage":["https://openalex.org/I93860229"]}],"countries":["IT"],"is_corresponding":true,"raw_author_name":"Antonino Tumeo","raw_affiliation_strings":["Politecnico di Milano, Milano, Italy"],"affiliations":[{"raw_affiliation_string":"Politecnico di Milano, Milano, Italy","institution_ids":["https://openalex.org/I93860229"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5072400487","display_name":"Christian Pilato","orcid":"https://orcid.org/0000-0001-9315-1788"},"institutions":[{"id":"https://openalex.org/I93860229","display_name":"Politecnico di Milano","ror":"https://ror.org/01nffqt88","country_code":"IT","type":"education","lineage":["https://openalex.org/I93860229"]}],"countries":["IT"],"is_corresponding":false,"raw_author_name":"Christian Pilato","raw_affiliation_strings":["Politecnico di Milano, Milano, Italy"],"affiliations":[{"raw_affiliation_string":"Politecnico di Milano, Milano, Italy","institution_ids":["https://openalex.org/I93860229"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5077005193","display_name":"Gianluca Palermo","orcid":"https://orcid.org/0000-0001-7955-8012"},"institutions":[{"id":"https://openalex.org/I93860229","display_name":"Politecnico di Milano","ror":"https://ror.org/01nffqt88","country_code":"IT","type":"education","lineage":["https://openalex.org/I93860229"]}],"countries":["IT"],"is_corresponding":false,"raw_author_name":"Gianluca Palermo","raw_affiliation_strings":["Politecnico di Milano, Milano, Italy"],"affiliations":[{"raw_affiliation_string":"Politecnico di Milano, Milano, Italy","institution_ids":["https://openalex.org/I93860229"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5028565685","display_name":"Fabrizio Ferrandi","orcid":"https://orcid.org/0000-0003-0301-4419"},"institutions":[{"id":"https://openalex.org/I93860229","display_name":"Politecnico di Milano","ror":"https://ror.org/01nffqt88","country_code":"IT","type":"education","lineage":["https://openalex.org/I93860229"]}],"countries":["IT"],"is_corresponding":false,"raw_author_name":"Fabrizio Ferrandi","raw_affiliation_strings":["Politecnico di Milano, Milano, Italy"],"affiliations":[{"raw_affiliation_string":"Politecnico di Milano, Milano, Italy","institution_ids":["https://openalex.org/I93860229"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5014181688","display_name":"Donatella Sciuto","orcid":"https://orcid.org/0000-0001-9030-6940"},"institutions":[{"id":"https://openalex.org/I93860229","display_name":"Politecnico di Milano","ror":"https://ror.org/01nffqt88","country_code":"IT","type":"education","lineage":["https://openalex.org/I93860229"]}],"countries":["IT"],"is_corresponding":false,"raw_author_name":"Donatella Sciuto","raw_affiliation_strings":["Politecnico di Milano, Milano, Italy"],"affiliations":[{"raw_affiliation_string":"Politecnico di Milano, Milano, Italy","institution_ids":["https://openalex.org/I93860229"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":5,"corresponding_author_ids":["https://openalex.org/A5041853964"],"corresponding_institution_ids":["https://openalex.org/I93860229"],"apc_list":null,"apc_paid":null,"fwci":2.6382,"has_fulltext":false,"cited_by_count":17,"citation_normalized_percentile":{"value":0.89975333,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":90,"max":96},"biblio":{"volume":null,"issue":null,"first_page":"265","last_page":"268"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9991999864578247,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9991999864578247,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9962000250816345,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.9961000084877014,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/microblaze","display_name":"MicroBlaze","score":0.9184114933013916},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.8145216703414917},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.781222939491272},{"id":"https://openalex.org/keywords/synchronization","display_name":"Synchronization (alternating current)","score":0.7519866228103638},{"id":"https://openalex.org/keywords/multiprocessing","display_name":"Multiprocessing","score":0.733960747718811},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.6155704259872437},{"id":"https://openalex.org/keywords/polling","display_name":"Polling","score":0.6050524711608887},{"id":"https://openalex.org/keywords/mpsoc","display_name":"MPSoC","score":0.48801103234291077},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.42229709029197693},{"id":"https://openalex.org/keywords/multi-core-processor","display_name":"Multi-core processor","score":0.4198184609413147},{"id":"https://openalex.org/keywords/operating-system","display_name":"Operating system","score":0.1434905230998993},{"id":"https://openalex.org/keywords/computer-network","display_name":"Computer network","score":0.06453853845596313}],"concepts":[{"id":"https://openalex.org/C2777575374","wikidata":"https://www.wikidata.org/wiki/Q1644704","display_name":"MicroBlaze","level":3,"score":0.9184114933013916},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.8145216703414917},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.781222939491272},{"id":"https://openalex.org/C2778562939","wikidata":"https://www.wikidata.org/wiki/Q1298791","display_name":"Synchronization (alternating current)","level":3,"score":0.7519866228103638},{"id":"https://openalex.org/C4822641","wikidata":"https://www.wikidata.org/wiki/Q846651","display_name":"Multiprocessing","level":2,"score":0.733960747718811},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.6155704259872437},{"id":"https://openalex.org/C204854418","wikidata":"https://www.wikidata.org/wiki/Q1362921","display_name":"Polling","level":2,"score":0.6050524711608887},{"id":"https://openalex.org/C2777187653","wikidata":"https://www.wikidata.org/wiki/Q975106","display_name":"MPSoC","level":3,"score":0.48801103234291077},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.42229709029197693},{"id":"https://openalex.org/C78766204","wikidata":"https://www.wikidata.org/wiki/Q555032","display_name":"Multi-core processor","level":2,"score":0.4198184609413147},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.1434905230998993},{"id":"https://openalex.org/C31258907","wikidata":"https://www.wikidata.org/wiki/Q1301371","display_name":"Computer network","level":1,"score":0.06453853845596313},{"id":"https://openalex.org/C127162648","wikidata":"https://www.wikidata.org/wiki/Q16858953","display_name":"Channel (broadcasting)","level":2,"score":0.0}],"mesh":[],"locations_count":2,"locations":[{"id":"doi:10.1145/1508128.1508174","is_oa":false,"landing_page_url":"https://doi.org/10.1145/1508128.1508174","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the ACM/SIGDA international symposium on Field programmable gate arrays","raw_type":"proceedings-article"},{"id":"pmh:oai:re.public.polimi.it:11311/553639","is_oa":false,"landing_page_url":"http://doi.acm.org/10.1145/1508128.1508174","pdf_url":null,"source":{"id":"https://openalex.org/S4306400312","display_name":"Virtual Community of Pathological Anatomy (University of Castilla La Mancha)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/I79189158","host_organization_name":"University of Castilla-La Mancha","host_organization_lineage":["https://openalex.org/I79189158"],"host_organization_lineage_names":[],"type":"repository"},"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"","raw_type":"info:eu-repo/semantics/conferenceObject"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":4,"referenced_works":["https://openalex.org/W2001738739","https://openalex.org/W2131017602","https://openalex.org/W2181544902","https://openalex.org/W2462402886"],"related_works":["https://openalex.org/W119521705","https://openalex.org/W4281711577","https://openalex.org/W2080926879","https://openalex.org/W2413864220","https://openalex.org/W2106200299","https://openalex.org/W2326041751","https://openalex.org/W2178653557","https://openalex.org/W2540211551","https://openalex.org/W2146938890","https://openalex.org/W2994908368"],"abstract_inverted_index":{"odern":[0],"Field":[1],"Programmable":[2],"Gate":[3],"Arrays":[4],"(FPGA)":[5],"can":[6,15],"be":[7,16],"programmed":[8],"with":[9,39,71],"multiple":[10],"soft-core":[11],"processors.":[12],"These":[13],"solutions":[14,87],"used":[17,52],"for":[18,25,67,77],"MultiProcessor":[19],"Systems-on-Chip":[20],"(MPSoCs)":[21],"prototyping":[22],"or":[23,74],"even":[24],"final":[26],"implementation.":[27],"Nevertheless,":[28],"efficient":[29],"synchronization":[30,65],"is":[31],"required":[32],"to":[33,88],"guarantee":[34],"performance":[35],"in":[36,53],"multiprocessing":[37],"environments":[38],"the":[40,54],"simple":[41],"cores":[42],"that":[43],"do":[44],"not":[45],"support":[46],"atomic":[47],"instructions":[48],"and":[49,79,81],"are":[50],"normally":[51],"standard":[55],"FPGA":[56],"toolchains.":[57],"In":[58],"this":[59],"paper,":[60],"we":[61],"introduce":[62],"two":[63],"hardware":[64],"modules":[66],"Xilinx":[68],"MicroBlaze":[69],"systems,":[70],"local":[72],"polling":[73],"queuing":[75],"mechanisms":[76],"locks":[78],"barriers,":[80],"present":[82],"a":[83],"comparison":[84],"of":[85],"these":[86],"alternative":[89],"designs.":[90]},"counts_by_year":[{"year":2024,"cited_by_count":1},{"year":2018,"cited_by_count":1},{"year":2017,"cited_by_count":2},{"year":2015,"cited_by_count":1},{"year":2013,"cited_by_count":2},{"year":2012,"cited_by_count":2}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}
