{"id":"https://openalex.org/W2030959856","doi":"https://doi.org/10.1145/1508128.1508160","title":"Intel\u00ae atom\u2122 processor core made FPGA-synthesizable","display_name":"Intel\u00ae atom\u2122 processor core made FPGA-synthesizable","publication_year":2009,"publication_date":"2009-02-22","ids":{"openalex":"https://openalex.org/W2030959856","doi":"https://doi.org/10.1145/1508128.1508160","mag":"2030959856"},"language":"en","primary_location":{"id":"doi:10.1145/1508128.1508160","is_oa":false,"landing_page_url":"https://doi.org/10.1145/1508128.1508160","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the ACM/SIGDA international symposium on Field programmable gate arrays","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5008708613","display_name":"Perry H. Wang","orcid":null},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":true,"raw_author_name":"Perry H. Wang","raw_affiliation_strings":["Intel, Santa Clara, CA, USA"],"affiliations":[{"raw_affiliation_string":"Intel, Santa Clara, CA, USA","institution_ids":["https://openalex.org/I1343180700"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5005994838","display_name":"Jamison D. Collins","orcid":null},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Jamison D. Collins","raw_affiliation_strings":["Intel, Santa Clara, CA, USA"],"affiliations":[{"raw_affiliation_string":"Intel, Santa Clara, CA, USA","institution_ids":["https://openalex.org/I1343180700"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5111955421","display_name":"Christopher Weaver","orcid":null},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Christopher T. Weaver","raw_affiliation_strings":["Intel, Austin, TX, USA"],"affiliations":[{"raw_affiliation_string":"Intel, Austin, TX, USA","institution_ids":["https://openalex.org/I1343180700"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5110056693","display_name":"Blliappa Kuttanna","orcid":null},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Blliappa Kuttanna","raw_affiliation_strings":["Intel, Austin, TX, USA"],"affiliations":[{"raw_affiliation_string":"Intel, Austin, TX, USA","institution_ids":["https://openalex.org/I1343180700"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5080248098","display_name":"Shahram Salamian","orcid":null},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Shahram Salamian","raw_affiliation_strings":["Intel, Austin, TX, USA"],"affiliations":[{"raw_affiliation_string":"Intel, Austin, TX, USA","institution_ids":["https://openalex.org/I1343180700"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5019370884","display_name":"Gautham N. Chinya","orcid":null},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Gautham N. Chinya","raw_affiliation_strings":["Intel, Hillsboro, OR, USA","Intel, Santa Clara, CA, USA"],"affiliations":[{"raw_affiliation_string":"Intel, Hillsboro, OR, USA","institution_ids":["https://openalex.org/I1343180700"]},{"raw_affiliation_string":"Intel, Santa Clara, CA, USA","institution_ids":["https://openalex.org/I1343180700"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5014543355","display_name":"Ethan Schuchman","orcid":null},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Ethan Schuchman","raw_affiliation_strings":["Intel, Santa Clara, CA, USA"],"affiliations":[{"raw_affiliation_string":"Intel, Santa Clara, CA, USA","institution_ids":["https://openalex.org/I1343180700"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5098142343","display_name":"Oliver Schilling","orcid":null},"institutions":[{"id":"https://openalex.org/I4210094487","display_name":"Intel (Germany)","ror":"https://ror.org/00m2x0g47","country_code":"DE","type":"company","lineage":["https://openalex.org/I1343180700","https://openalex.org/I4210094487"]}],"countries":["DE"],"is_corresponding":false,"raw_author_name":"Oliver Schilling","raw_affiliation_strings":["Intel, Braunschweig, Germany"],"affiliations":[{"raw_affiliation_string":"Intel, Braunschweig, Germany","institution_ids":["https://openalex.org/I4210094487"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5098253580","display_name":"Thorsten Doil","orcid":null},"institutions":[{"id":"https://openalex.org/I4210094487","display_name":"Intel (Germany)","ror":"https://ror.org/00m2x0g47","country_code":"DE","type":"company","lineage":["https://openalex.org/I1343180700","https://openalex.org/I4210094487"]}],"countries":["DE"],"is_corresponding":false,"raw_author_name":"Thorsten Doil","raw_affiliation_strings":["Intel, Braunschweig, Germany"],"affiliations":[{"raw_affiliation_string":"Intel, Braunschweig, Germany","institution_ids":["https://openalex.org/I4210094487"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5017225851","display_name":"Sebastian Steibl","orcid":null},"institutions":[{"id":"https://openalex.org/I4210094487","display_name":"Intel (Germany)","ror":"https://ror.org/00m2x0g47","country_code":"DE","type":"company","lineage":["https://openalex.org/I1343180700","https://openalex.org/I4210094487"]}],"countries":["DE"],"is_corresponding":false,"raw_author_name":"Sebastian Steibl","raw_affiliation_strings":["Intel, Braunschweig, Germany"],"affiliations":[{"raw_affiliation_string":"Intel, Braunschweig, Germany","institution_ids":["https://openalex.org/I4210094487"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5100371015","display_name":"Hong Wang","orcid":"https://orcid.org/0009-0008-2874-2168"},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Hong Wang","raw_affiliation_strings":["Intel, Santa Clara, CA, USA"],"affiliations":[{"raw_affiliation_string":"Intel, Santa Clara, CA, USA","institution_ids":["https://openalex.org/I1343180700"]}]}],"institutions":[],"countries_distinct_count":2,"institutions_distinct_count":11,"corresponding_author_ids":["https://openalex.org/A5008708613"],"corresponding_institution_ids":["https://openalex.org/I1343180700"],"apc_list":null,"apc_paid":null,"fwci":7.3234,"has_fulltext":false,"cited_by_count":69,"citation_normalized_percentile":{"value":0.97538314,"is_in_top_1_percent":false,"is_in_top_10_percent":true},"cited_by_percentile_year":{"min":89,"max":100},"biblio":{"volume":null,"issue":null,"first_page":null,"last_page":null},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9995999932289124,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.9990000128746033,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.7030101418495178},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.6551552414894104},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.5117621421813965},{"id":"https://openalex.org/keywords/multi-core-processor","display_name":"Multi-core processor","score":0.498598575592041},{"id":"https://openalex.org/keywords/atom","display_name":"Atom (system on chip)","score":0.467373788356781},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.4413793087005615},{"id":"https://openalex.org/keywords/core","display_name":"Core (optical fiber)","score":0.424347460269928},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.3976793587207794},{"id":"https://openalex.org/keywords/telecommunications","display_name":"Telecommunications","score":0.06627440452575684}],"concepts":[{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.7030101418495178},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6551552414894104},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.5117621421813965},{"id":"https://openalex.org/C78766204","wikidata":"https://www.wikidata.org/wiki/Q555032","display_name":"Multi-core processor","level":2,"score":0.498598575592041},{"id":"https://openalex.org/C58312451","wikidata":"https://www.wikidata.org/wiki/Q4817200","display_name":"Atom (system on chip)","level":2,"score":0.467373788356781},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.4413793087005615},{"id":"https://openalex.org/C2164484","wikidata":"https://www.wikidata.org/wiki/Q5170150","display_name":"Core (optical fiber)","level":2,"score":0.424347460269928},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.3976793587207794},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.06627440452575684}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1145/1508128.1508160","is_oa":false,"landing_page_url":"https://doi.org/10.1145/1508128.1508160","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the ACM/SIGDA international symposium on Field programmable gate arrays","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"id":"https://metadata.un.org/sdg/9","score":0.4300000071525574,"display_name":"Industry, innovation and infrastructure"}],"awards":[],"funders":[{"id":"https://openalex.org/F4320330412","display_name":"Scheme for Promotion of Academic and Research Collaboration","ror":null}],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":16,"referenced_works":["https://openalex.org/W138399915","https://openalex.org/W1479813523","https://openalex.org/W1537307653","https://openalex.org/W1968621231","https://openalex.org/W1999777350","https://openalex.org/W2022807575","https://openalex.org/W2059817063","https://openalex.org/W2097181398","https://openalex.org/W2109907925","https://openalex.org/W2115753002","https://openalex.org/W2140781161","https://openalex.org/W2141424374","https://openalex.org/W2148658001","https://openalex.org/W2151181453","https://openalex.org/W2171697422","https://openalex.org/W3140285646"],"related_works":["https://openalex.org/W2488897859","https://openalex.org/W2366027386","https://openalex.org/W164750744","https://openalex.org/W2995926156","https://openalex.org/W2063534976","https://openalex.org/W2284838239","https://openalex.org/W2372170743","https://openalex.org/W3106220299","https://openalex.org/W2365995233","https://openalex.org/W1566136542"],"abstract_inverted_index":{"We":[0],"present":[1],"an":[2,97],"FPGA-synthesizable":[3,50],"version":[4],"of":[5,81,106,150],"the":[6,21,40,54,65,82,87,93,104,107,117,138],"Intel":[7],"Atom":[8,23,83,94,119,132],"processor":[9,120],"core,":[10],"synthesized":[11],"to":[12,101,122],"a":[13,61,71,125],"Virtex-5":[14,127],"based":[15],"FPGA":[16,56],"emulation":[17],"system.":[18],"To":[19],"make":[20],"production":[22],"design":[24],"in":[25,39,92,115],"SystemVerilog":[26],"synthesizable":[27,131],"through":[28],"industry":[29],"standard":[30,162],"EDA":[31],"tool":[32],"flow,":[33],"we":[34,85,113],"transformed":[35],"and":[36,45,156,160],"mapped":[37],"latches":[38],"design,":[41],"converted":[42],"clock":[43],"gating,":[44],"replaced":[46,86],"nonsynthesizable":[47],"constructs":[48],"with":[49,64,96,103,142],"counterparts.":[51],"Additionally,":[52],"as":[53],"target":[55],"emulator":[57],"is":[58,148],"hosted":[59],"on":[60,137],"PC":[62,108,140],"platform":[63],"Pentium-based":[66],"CPU":[67],"socket":[68],"that":[69,80],"supports":[70],"significantly":[72],"different":[73],"front":[74],"side":[75],"bus":[76,89],"(FSB)":[77],"protocol":[78,100],"from":[79],"processor,":[84],"existing":[88],"control":[90],"logic":[91],"core":[95,121,133],"alternate":[98],"FSB":[99],"communicate":[102],"rest":[105],"platform.":[109],"With":[110],"these":[111],"efforts,":[112],"succeeded":[114],"synthesizing":[116],"entire":[118],"fit":[123],"within":[124],"single":[126],"LX330":[128],"FPGA.":[129],"The":[130],"runs":[134],"at":[135],"50Mhz":[136],"Pentium":[139],"motherboard":[141],"fully":[143],"functional":[144],"I/O":[145],"peripherals.":[146],"It":[147],"capable":[149],"booting":[151],"off-the-shelf":[152],"MS-DOS,":[153],"Windows":[154],"XP":[155],"Linux":[157],"operating":[158],"systems,":[159],"executing":[161],"x86":[163],"workloads.":[164]},"counts_by_year":[{"year":2022,"cited_by_count":1},{"year":2021,"cited_by_count":1},{"year":2020,"cited_by_count":4},{"year":2019,"cited_by_count":3},{"year":2018,"cited_by_count":4},{"year":2017,"cited_by_count":6},{"year":2016,"cited_by_count":5},{"year":2015,"cited_by_count":9},{"year":2014,"cited_by_count":3},{"year":2013,"cited_by_count":6},{"year":2012,"cited_by_count":13}],"updated_date":"2026-03-20T23:20:44.827607","created_date":"2025-10-10T00:00:00"}
