{"id":"https://openalex.org/W2003435315","doi":"https://doi.org/10.1145/1508128.1508151","title":"FPGA technology mapping with encoded libraries andstaged priority cuts","display_name":"FPGA technology mapping with encoded libraries andstaged priority cuts","publication_year":2009,"publication_date":"2009-02-22","ids":{"openalex":"https://openalex.org/W2003435315","doi":"https://doi.org/10.1145/1508128.1508151","mag":"2003435315"},"language":"en","primary_location":{"id":"doi:10.1145/1508128.1508151","is_oa":false,"landing_page_url":"https://doi.org/10.1145/1508128.1508151","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the ACM/SIGDA international symposium on Field programmable gate arrays","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5007026340","display_name":"Andrew Kennings","orcid":null},"institutions":[],"countries":[],"is_corresponding":true,"raw_author_name":"Andrew Kennings","raw_affiliation_strings":["Actel Corporation, Mountain View, CA, USA"],"affiliations":[{"raw_affiliation_string":"Actel Corporation, Mountain View, CA, USA","institution_ids":[]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5005615652","display_name":"Kristofer Vorwerk","orcid":null},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"Kristofer Vorwerk","raw_affiliation_strings":["Actel Corporation, Mountain View, CA, USA"],"affiliations":[{"raw_affiliation_string":"Actel Corporation, Mountain View, CA, USA","institution_ids":[]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5111625464","display_name":"Arun Kundu","orcid":null},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"Arun Kundu","raw_affiliation_strings":["Actel Corporation, Mountain View, CA, USA"],"affiliations":[{"raw_affiliation_string":"Actel Corporation, Mountain View, CA, USA","institution_ids":[]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5070951209","display_name":"Val Pevzner","orcid":null},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"Val Pevzner","raw_affiliation_strings":["Actel Corporation, Mountain View, CA, USA"],"affiliations":[{"raw_affiliation_string":"Actel Corporation, Mountain View, CA, USA","institution_ids":[]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5025559864","display_name":"Andy Fox","orcid":null},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"Andy Fox","raw_affiliation_strings":["Actel Corporation, Mountain View, CA, USA"],"affiliations":[{"raw_affiliation_string":"Actel Corporation, Mountain View, CA, USA","institution_ids":[]}]}],"institutions":[],"countries_distinct_count":0,"institutions_distinct_count":5,"corresponding_author_ids":["https://openalex.org/A5007026340"],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":2.6382,"has_fulltext":false,"cited_by_count":11,"citation_normalized_percentile":{"value":0.90103601,"is_in_top_1_percent":false,"is_in_top_10_percent":true},"cited_by_percentile_year":{"min":89,"max":94},"biblio":{"volume":null,"issue":null,"first_page":"143","last_page":"150"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9993000030517578,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.8868143558502197},{"id":"https://openalex.org/keywords/lookup-table","display_name":"Lookup table","score":0.8837113976478577},{"id":"https://openalex.org/keywords/logic-block","display_name":"Logic block","score":0.8278625011444092},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7216782569885254},{"id":"https://openalex.org/keywords/logic-synthesis","display_name":"Logic synthesis","score":0.5970580577850342},{"id":"https://openalex.org/keywords/simple","display_name":"Simple (philosophy)","score":0.5234096646308899},{"id":"https://openalex.org/keywords/block","display_name":"Block (permutation group theory)","score":0.5176439881324768},{"id":"https://openalex.org/keywords/logic-gate","display_name":"Logic gate","score":0.5077041387557983},{"id":"https://openalex.org/keywords/logic-optimization","display_name":"Logic optimization","score":0.5021154880523682},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.49171000719070435},{"id":"https://openalex.org/keywords/logic-family","display_name":"Logic family","score":0.43736231327056885},{"id":"https://openalex.org/keywords/programmable-logic-array","display_name":"Programmable logic array","score":0.42081180214881897},{"id":"https://openalex.org/keywords/programmable-logic-device","display_name":"Programmable logic device","score":0.4190133213996887},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.3897756338119507},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.37585368752479553},{"id":"https://openalex.org/keywords/computer-engineering","display_name":"Computer engineering","score":0.34463536739349365},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.3365527093410492},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.28942564129829407},{"id":"https://openalex.org/keywords/mathematics","display_name":"Mathematics","score":0.1606619954109192}],"concepts":[{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.8868143558502197},{"id":"https://openalex.org/C134835016","wikidata":"https://www.wikidata.org/wiki/Q690265","display_name":"Lookup table","level":2,"score":0.8837113976478577},{"id":"https://openalex.org/C2778325283","wikidata":"https://www.wikidata.org/wiki/Q1125244","display_name":"Logic block","level":3,"score":0.8278625011444092},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7216782569885254},{"id":"https://openalex.org/C157922185","wikidata":"https://www.wikidata.org/wiki/Q173198","display_name":"Logic synthesis","level":3,"score":0.5970580577850342},{"id":"https://openalex.org/C2780586882","wikidata":"https://www.wikidata.org/wiki/Q7520643","display_name":"Simple (philosophy)","level":2,"score":0.5234096646308899},{"id":"https://openalex.org/C2777210771","wikidata":"https://www.wikidata.org/wiki/Q4927124","display_name":"Block (permutation group theory)","level":2,"score":0.5176439881324768},{"id":"https://openalex.org/C131017901","wikidata":"https://www.wikidata.org/wiki/Q170451","display_name":"Logic gate","level":2,"score":0.5077041387557983},{"id":"https://openalex.org/C28449271","wikidata":"https://www.wikidata.org/wiki/Q6667469","display_name":"Logic optimization","level":4,"score":0.5021154880523682},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.49171000719070435},{"id":"https://openalex.org/C162454741","wikidata":"https://www.wikidata.org/wiki/Q173359","display_name":"Logic family","level":4,"score":0.43736231327056885},{"id":"https://openalex.org/C182322920","wikidata":"https://www.wikidata.org/wiki/Q2112217","display_name":"Programmable logic array","level":3,"score":0.42081180214881897},{"id":"https://openalex.org/C206274596","wikidata":"https://www.wikidata.org/wiki/Q1063837","display_name":"Programmable logic device","level":2,"score":0.4190133213996887},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.3897756338119507},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.37585368752479553},{"id":"https://openalex.org/C113775141","wikidata":"https://www.wikidata.org/wiki/Q428691","display_name":"Computer engineering","level":1,"score":0.34463536739349365},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.3365527093410492},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.28942564129829407},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.1606619954109192},{"id":"https://openalex.org/C2524010","wikidata":"https://www.wikidata.org/wiki/Q8087","display_name":"Geometry","level":1,"score":0.0},{"id":"https://openalex.org/C138885662","wikidata":"https://www.wikidata.org/wiki/Q5891","display_name":"Philosophy","level":0,"score":0.0},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.0},{"id":"https://openalex.org/C111472728","wikidata":"https://www.wikidata.org/wiki/Q9471","display_name":"Epistemology","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1145/1508128.1508151","is_oa":false,"landing_page_url":"https://doi.org/10.1145/1508128.1508151","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the ACM/SIGDA international symposium on Field programmable gate arrays","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"id":"https://metadata.un.org/sdg/9","display_name":"Industry, innovation and infrastructure","score":0.6000000238418579}],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":26,"referenced_works":["https://openalex.org/W1480183640","https://openalex.org/W1612810659","https://openalex.org/W1905608265","https://openalex.org/W1985457698","https://openalex.org/W2035561773","https://openalex.org/W2052067881","https://openalex.org/W2089442786","https://openalex.org/W2096466247","https://openalex.org/W2099134576","https://openalex.org/W2100955320","https://openalex.org/W2105715355","https://openalex.org/W2108508582","https://openalex.org/W2116094656","https://openalex.org/W2118988958","https://openalex.org/W2122498441","https://openalex.org/W2133743520","https://openalex.org/W2134060873","https://openalex.org/W2139026138","https://openalex.org/W2145206729","https://openalex.org/W2150484863","https://openalex.org/W2150787480","https://openalex.org/W2159111323","https://openalex.org/W2163492764","https://openalex.org/W2294502317","https://openalex.org/W4240866746","https://openalex.org/W6674369357"],"related_works":["https://openalex.org/W2994343469","https://openalex.org/W3105918491","https://openalex.org/W1905312773","https://openalex.org/W2167086449","https://openalex.org/W2102777336","https://openalex.org/W2477544739","https://openalex.org/W2139569078","https://openalex.org/W4252227487","https://openalex.org/W2141429499","https://openalex.org/W4248303983"],"abstract_inverted_index":{"Technology":[0],"mapping":[1,33],"is":[2,18,57],"an":[3,36],"important":[4],"step":[5],"in":[6,11],"the":[7,54,75],"FPGA":[8,37,88],"CAD":[9],"flow":[10],"which":[12,42],"a":[13,21,30,45,58,86],"network":[14,22],"of":[15,23,39,47,49,77],"simple":[16],"gates":[17],"converted":[19],"into":[20],"logic":[24,40,55],"blocks.":[25],"We":[26],"consider":[27],"enhancements":[28],"to":[29,51,73,85],"traditional":[31],"LUT-based":[32],"algorithm":[34],"for":[35],"comprised":[38],"blocks":[41],"implement":[43],"only":[44],"subset":[46],"functions":[48],"up":[50],"k":[52],"variables--specifically,":[53],"block":[56],"partial":[59],"LUT,":[60],"but":[61],"it":[62],"possesses":[63],"more":[64],"inputs":[65],"than":[66],"typical":[67],"LUTs.":[68],"Numerical":[69],"results":[70],"are":[71],"presented":[72],"demonstrate":[74],"efficacy":[76],"our":[78],"proposed":[79],"techniques":[80],"using":[81],"real":[82],"circuits":[83],"mapped":[84],"commercial":[87],"architecture.":[89]},"counts_by_year":[{"year":2013,"cited_by_count":1},{"year":2012,"cited_by_count":1}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}