{"id":"https://openalex.org/W2123491437","doi":"https://doi.org/10.1145/1508128.1508132","title":"Clock power reduction for virtex-5 FPGAs","display_name":"Clock power reduction for virtex-5 FPGAs","publication_year":2009,"publication_date":"2009-02-22","ids":{"openalex":"https://openalex.org/W2123491437","doi":"https://doi.org/10.1145/1508128.1508132","mag":"2123491437"},"language":"en","primary_location":{"id":"doi:10.1145/1508128.1508132","is_oa":false,"landing_page_url":"https://doi.org/10.1145/1508128.1508132","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the ACM/SIGDA international symposium on Field programmable gate arrays","raw_type":"proceedings-article"},"type":"conference-paper","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5101934328","display_name":"Qiang Wang","orcid":"https://orcid.org/0000-0002-2416-1832"},"institutions":[{"id":"https://openalex.org/I32923980","display_name":"Xilinx (United States)","ror":"https://ror.org/01rb7bk56","country_code":"US","type":"company","lineage":["https://openalex.org/I32923980"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Qiang Wang","raw_affiliation_strings":["Xilinx, Inc., San Jose, CA, USA","Xilinx Inc, San Jose, CA, USA#TAB#"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Xilinx, Inc., San Jose, CA, USA","institution_ids":["https://openalex.org/I32923980"]},{"raw_affiliation_string":"Xilinx Inc, San Jose, CA, USA#TAB#","institution_ids":["https://openalex.org/I32923980"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5103737916","display_name":"Subodh Gupta","orcid":null},"institutions":[{"id":"https://openalex.org/I32923980","display_name":"Xilinx (United States)","ror":"https://ror.org/01rb7bk56","country_code":"US","type":"company","lineage":["https://openalex.org/I32923980"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Subodh Gupta","raw_affiliation_strings":["Xilinx, Inc., San Jose, CA, USA","Xilinx Inc, San Jose, CA, USA#TAB#"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Xilinx, Inc., San Jose, CA, USA","institution_ids":["https://openalex.org/I32923980"]},{"raw_affiliation_string":"Xilinx Inc, San Jose, CA, USA#TAB#","institution_ids":["https://openalex.org/I32923980"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5102812429","display_name":"Jason H. Anderson","orcid":"https://orcid.org/0000-0001-9083-6853"},"institutions":[{"id":"https://openalex.org/I185261750","display_name":"University of Toronto","ror":"https://ror.org/03dbr7087","country_code":"CA","type":"education","lineage":["https://openalex.org/I185261750"]}],"countries":["CA"],"is_corresponding":false,"raw_author_name":"Jason H. Anderson","raw_affiliation_strings":["University of Toronto, Toronto, ON, Canada","University of Toronto, Toronto, On, Canada"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"University of Toronto, Toronto, ON, Canada","institution_ids":["https://openalex.org/I185261750"]},{"raw_affiliation_string":"University of Toronto, Toronto, On, Canada","institution_ids":["https://openalex.org/I185261750"]}]}],"institutions":[],"countries_distinct_count":2,"institutions_distinct_count":2,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":11.1647,"has_fulltext":false,"cited_by_count":40,"citation_normalized_percentile":{"value":0.99167837,"is_in_top_1_percent":true,"is_in_top_10_percent":true},"cited_by_percentile_year":{"min":90,"max":98},"biblio":{"volume":null,"issue":null,"first_page":"13","last_page":"22"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/clock-gating","display_name":"Clock gating","score":0.9275228381156921},{"id":"https://openalex.org/keywords/clock-network","display_name":"Clock network","score":0.8810443878173828},{"id":"https://openalex.org/keywords/cpu-multiplier","display_name":"CPU multiplier","score":0.808225154876709},{"id":"https://openalex.org/keywords/digital-clock-manager","display_name":"Digital clock manager","score":0.805752694606781},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.8036555051803589},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.6469472050666809},{"id":"https://openalex.org/keywords/clock-domain-crossing","display_name":"Clock domain crossing","score":0.5380868911743164},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.5155901312828064},{"id":"https://openalex.org/keywords/virtex","display_name":"Virtex","score":0.46493715047836304},{"id":"https://openalex.org/keywords/reduction","display_name":"Reduction (mathematics)","score":0.4616042971611023},{"id":"https://openalex.org/keywords/clock-rate","display_name":"Clock rate","score":0.4591398239135742},{"id":"https://openalex.org/keywords/dynamic-demand","display_name":"Dynamic demand","score":0.4476274847984314},{"id":"https://openalex.org/keywords/application-specific-integrated-circuit","display_name":"Application-specific integrated circuit","score":0.4269551932811737},{"id":"https://openalex.org/keywords/clock-skew","display_name":"Clock skew","score":0.37950819730758667},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.3458993434906006},{"id":"https://openalex.org/keywords/synchronous-circuit","display_name":"Synchronous circuit","score":0.33594778180122375},{"id":"https://openalex.org/keywords/power","display_name":"Power (physics)","score":0.3312976360321045},{"id":"https://openalex.org/keywords/clock-signal","display_name":"Clock signal","score":0.13639548420906067},{"id":"https://openalex.org/keywords/telecommunications","display_name":"Telecommunications","score":0.0835466980934143}],"concepts":[{"id":"https://openalex.org/C22716491","wikidata":"https://www.wikidata.org/wiki/Q590170","display_name":"Clock gating","level":5,"score":0.9275228381156921},{"id":"https://openalex.org/C2778182565","wikidata":"https://www.wikidata.org/wiki/Q1752879","display_name":"Clock network","level":5,"score":0.8810443878173828},{"id":"https://openalex.org/C125576049","wikidata":"https://www.wikidata.org/wiki/Q2246273","display_name":"CPU multiplier","level":5,"score":0.808225154876709},{"id":"https://openalex.org/C113074038","wikidata":"https://www.wikidata.org/wiki/Q5276052","display_name":"Digital clock manager","level":5,"score":0.805752694606781},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.8036555051803589},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6469472050666809},{"id":"https://openalex.org/C127204226","wikidata":"https://www.wikidata.org/wiki/Q5134799","display_name":"Clock domain crossing","level":5,"score":0.5380868911743164},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.5155901312828064},{"id":"https://openalex.org/C2777674469","wikidata":"https://www.wikidata.org/wiki/Q20741011","display_name":"Virtex","level":3,"score":0.46493715047836304},{"id":"https://openalex.org/C111335779","wikidata":"https://www.wikidata.org/wiki/Q3454686","display_name":"Reduction (mathematics)","level":2,"score":0.4616042971611023},{"id":"https://openalex.org/C178693496","wikidata":"https://www.wikidata.org/wiki/Q911691","display_name":"Clock rate","level":3,"score":0.4591398239135742},{"id":"https://openalex.org/C45872418","wikidata":"https://www.wikidata.org/wiki/Q5318966","display_name":"Dynamic demand","level":3,"score":0.4476274847984314},{"id":"https://openalex.org/C77390884","wikidata":"https://www.wikidata.org/wiki/Q217302","display_name":"Application-specific integrated circuit","level":2,"score":0.4269551932811737},{"id":"https://openalex.org/C60501442","wikidata":"https://www.wikidata.org/wiki/Q4382014","display_name":"Clock skew","level":4,"score":0.37950819730758667},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.3458993434906006},{"id":"https://openalex.org/C42196554","wikidata":"https://www.wikidata.org/wiki/Q1186179","display_name":"Synchronous circuit","level":4,"score":0.33594778180122375},{"id":"https://openalex.org/C163258240","wikidata":"https://www.wikidata.org/wiki/Q25342","display_name":"Power (physics)","level":2,"score":0.3312976360321045},{"id":"https://openalex.org/C137059387","wikidata":"https://www.wikidata.org/wiki/Q426882","display_name":"Clock signal","level":3,"score":0.13639548420906067},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.0835466980934143},{"id":"https://openalex.org/C165005293","wikidata":"https://www.wikidata.org/wiki/Q1074500","display_name":"Chip","level":2,"score":0.0},{"id":"https://openalex.org/C134652429","wikidata":"https://www.wikidata.org/wiki/Q1052698","display_name":"Jitter","level":2,"score":0.0},{"id":"https://openalex.org/C121332964","wikidata":"https://www.wikidata.org/wiki/Q413","display_name":"Physics","level":0,"score":0.0},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.0},{"id":"https://openalex.org/C62520636","wikidata":"https://www.wikidata.org/wiki/Q944","display_name":"Quantum mechanics","level":1,"score":0.0},{"id":"https://openalex.org/C2524010","wikidata":"https://www.wikidata.org/wiki/Q8087","display_name":"Geometry","level":1,"score":0.0}],"mesh":[],"locations_count":2,"locations":[{"id":"doi:10.1145/1508128.1508132","is_oa":false,"landing_page_url":"https://doi.org/10.1145/1508128.1508132","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the ACM/SIGDA international symposium on Field programmable gate arrays","raw_type":"proceedings-article"},{"id":"pmh:oai:CiteSeerX.psu:10.1.1.564.6980","is_oa":false,"landing_page_url":"http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.564.6980","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"http://www.janders.ca/fpga55-wang.pdf","raw_type":"text"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":32,"referenced_works":["https://openalex.org/W1515491391","https://openalex.org/W1938409394","https://openalex.org/W1977850862","https://openalex.org/W1992976995","https://openalex.org/W2001576395","https://openalex.org/W2001824086","https://openalex.org/W2022698427","https://openalex.org/W2029541370","https://openalex.org/W2033685698","https://openalex.org/W2095310213","https://openalex.org/W2097521167","https://openalex.org/W2101356024","https://openalex.org/W2111515250","https://openalex.org/W2113735758","https://openalex.org/W2122830930","https://openalex.org/W2123163878","https://openalex.org/W2124021899","https://openalex.org/W2137663768","https://openalex.org/W2137769675","https://openalex.org/W2137978438","https://openalex.org/W2141752451","https://openalex.org/W2143629014","https://openalex.org/W2143880270","https://openalex.org/W2149513075","https://openalex.org/W2150549968","https://openalex.org/W2155033206","https://openalex.org/W2159142998","https://openalex.org/W2161531333","https://openalex.org/W2162969296","https://openalex.org/W2163108907","https://openalex.org/W2170510975","https://openalex.org/W4230090919"],"related_works":["https://openalex.org/W2474747038","https://openalex.org/W2088914741","https://openalex.org/W2559451387","https://openalex.org/W4247180033","https://openalex.org/W2137310043","https://openalex.org/W3006003651","https://openalex.org/W2337711143","https://openalex.org/W2090213929","https://openalex.org/W3199387640","https://openalex.org/W2617666058"],"abstract_inverted_index":{"Clock":[0,90],"network":[1],"power":[2,16,43,69,121],"in":[3,18,29,41],"field-programmable":[4],"gate":[5],"arrays":[6],"(FPGAs)":[7],"is":[8],"considered":[9],"and":[10,68,85,119],"two":[11],"complementary":[12],"approaches":[13,26],"for":[14],"clock":[15,47,63,102,109,117],"reduction":[17],"the":[19,46,62,77,82,100,106,116],"Xilinx":[20],"Virtex-5":[21,37],"FPGA":[22],"are":[23,27,95,127],"presented.":[24],"The":[25,49,73],"unique":[28],"that":[30],"they":[31],"leverage":[32],"specific":[33],"architectural":[34],"aspects":[35],"of":[36],"to":[38,56,71,88,98,112,123],"achieve":[39],"reductions":[40,126],"dynamic":[42],"consumed":[44],"by":[45],"network.":[48],"first":[50],"approach":[51,75],"comprises":[52],"a":[53],"placement-based":[54],"technique":[55],"reduce":[57],"interconnect":[58,118],"resource":[59],"usage":[60],"on":[61,93,105,115,133],"network,":[64,110],"thereby":[65],"reducing":[66],"capacitance":[67],"(up":[70,122],"12%).":[72],"second":[74],"borrows":[76],"\"clock":[78],"gating\"":[79],"notion":[80],"from":[81],"ASIC":[83],"domain":[84],"applies":[86],"it":[87],"FPGAs.":[89],"enable":[91,103],"signals":[92],"flip-flops":[94],"selectively":[96],"migrated":[97],"use":[99],"dedicated":[101],"available":[104],"FPGA's":[107],"built-in":[108],"leading":[111],"reduced":[113],"toggling":[114],"lower":[120],"28%).":[124],"Power":[125],"achieved":[128],"without":[129],"any":[130],"performance":[131],"penalty,":[132],"average.":[134]},"counts_by_year":[{"year":2025,"cited_by_count":1},{"year":2024,"cited_by_count":1},{"year":2020,"cited_by_count":3},{"year":2019,"cited_by_count":2},{"year":2018,"cited_by_count":2},{"year":2016,"cited_by_count":1},{"year":2015,"cited_by_count":2},{"year":2013,"cited_by_count":5},{"year":2012,"cited_by_count":4}],"updated_date":"2026-07-29T14:22:42.915294","created_date":"2025-10-10T00:00:00"}