{"id":"https://openalex.org/W2117610141","doi":"https://doi.org/10.1145/1504176.1504220","title":"NePalTM","display_name":"NePalTM","publication_year":2009,"publication_date":"2009-02-14","ids":{"openalex":"https://openalex.org/W2117610141","doi":"https://doi.org/10.1145/1504176.1504220","mag":"2117610141"},"language":"en","primary_location":{"id":"doi:10.1145/1504176.1504220","is_oa":false,"landing_page_url":"https://doi.org/10.1145/1504176.1504220","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 14th ACM SIGPLAN symposium on Principles and practice of parallel programming","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5037131742","display_name":"Haris Volos","orcid":"https://orcid.org/0000-0002-3777-0012"},"institutions":[{"id":"https://openalex.org/I135310074","display_name":"University of Wisconsin\u2013Madison","ror":"https://ror.org/01y2jtd41","country_code":"US","type":"education","lineage":["https://openalex.org/I135310074"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Haris Volos","raw_affiliation_strings":["University of Wisconsin, Madison, WI, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"University of Wisconsin, Madison, WI, USA","institution_ids":["https://openalex.org/I135310074"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5078668785","display_name":"Adam Welc","orcid":"https://orcid.org/0009-0005-0515-4994"},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Adam Welc","raw_affiliation_strings":["Intel Corporation, Santa Clara, CA, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Intel Corporation, Santa Clara, CA, USA","institution_ids":["https://openalex.org/I1343180700"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5007158460","display_name":"Ali-Reza Adl-Tabatabai","orcid":null},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Ali-Reza Adl-Tabatabai","raw_affiliation_strings":["Intel Corporation, Santa Clara, CA, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Intel Corporation, Santa Clara, CA, USA","institution_ids":["https://openalex.org/I1343180700"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5076969648","display_name":"Tatiana Shpeisman","orcid":"https://orcid.org/0000-0002-4225-8734"},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Tatiana Shpeisman","raw_affiliation_strings":["Intel Corporation, Santa Clara, CA, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Intel Corporation, Santa Clara, CA, USA","institution_ids":["https://openalex.org/I1343180700"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5101131112","display_name":"Xinmin Tian","orcid":null},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Xinmin Tian","raw_affiliation_strings":["Intel Corporation, Santa Clara, CA, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Intel Corporation, Santa Clara, CA, USA","institution_ids":["https://openalex.org/I1343180700"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5087985063","display_name":"Ravi Narayanaswamy","orcid":null},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Ravi Narayanaswamy","raw_affiliation_strings":["Intel Corporation, Santa Clara, CA, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Intel Corporation, Santa Clara, CA, USA","institution_ids":["https://openalex.org/I1343180700"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":6,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":2.1773,"has_fulltext":false,"cited_by_count":18,"citation_normalized_percentile":{"value":0.88598452,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":98},"biblio":{"volume":null,"issue":null,"first_page":"291","last_page":"292"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10772","display_name":"Distributed systems and fault tolerance","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10772","display_name":"Distributed systems and fault tolerance","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9902999997138977,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11181","display_name":"Advanced Data Storage Technologies","score":0.9848999977111816,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.8233792781829834},{"id":"https://openalex.org/keywords/transactional-memory","display_name":"Transactional memory","score":0.6958776116371155},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.6902623176574707},{"id":"https://openalex.org/keywords/concurrency-control","display_name":"Concurrency control","score":0.6662908792495728},{"id":"https://openalex.org/keywords/concurrency","display_name":"Concurrency","score":0.6451952457427979},{"id":"https://openalex.org/keywords/parallelism","display_name":"Parallelism (grammar)","score":0.6443418264389038},{"id":"https://openalex.org/keywords/programming-language","display_name":"Programming language","score":0.565772533416748},{"id":"https://openalex.org/keywords/multiversion-concurrency-control","display_name":"Multiversion concurrency control","score":0.5592223405838013},{"id":"https://openalex.org/keywords/optimistic-concurrency-control","display_name":"Optimistic concurrency control","score":0.4671195447444916},{"id":"https://openalex.org/keywords/concurrent-computing","display_name":"Concurrent computing","score":0.42817503213882446},{"id":"https://openalex.org/keywords/distributed-concurrency-control","display_name":"Distributed concurrency control","score":0.23125478625297546}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.8233792781829834},{"id":"https://openalex.org/C134277064","wikidata":"https://www.wikidata.org/wiki/Q878206","display_name":"Transactional memory","level":3,"score":0.6958776116371155},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.6902623176574707},{"id":"https://openalex.org/C84511453","wikidata":"https://www.wikidata.org/wiki/Q2914952","display_name":"Concurrency control","level":3,"score":0.6662908792495728},{"id":"https://openalex.org/C193702766","wikidata":"https://www.wikidata.org/wiki/Q1414548","display_name":"Concurrency","level":2,"score":0.6451952457427979},{"id":"https://openalex.org/C2781172179","wikidata":"https://www.wikidata.org/wiki/Q853109","display_name":"Parallelism (grammar)","level":2,"score":0.6443418264389038},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.565772533416748},{"id":"https://openalex.org/C108744092","wikidata":"https://www.wikidata.org/wiki/Q93695","display_name":"Multiversion concurrency control","level":5,"score":0.5592223405838013},{"id":"https://openalex.org/C79240183","wikidata":"https://www.wikidata.org/wiki/Q1779327","display_name":"Optimistic concurrency control","level":5,"score":0.4671195447444916},{"id":"https://openalex.org/C150495011","wikidata":"https://www.wikidata.org/wiki/Q128392","display_name":"Concurrent computing","level":2,"score":0.42817503213882446},{"id":"https://openalex.org/C208087996","wikidata":"https://www.wikidata.org/wiki/Q5283142","display_name":"Distributed concurrency control","level":4,"score":0.23125478625297546},{"id":"https://openalex.org/C75949130","wikidata":"https://www.wikidata.org/wiki/Q848010","display_name":"Database transaction","level":2,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1145/1504176.1504220","is_oa":false,"landing_page_url":"https://doi.org/10.1145/1504176.1504220","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 14th ACM SIGPLAN symposium on Principles and practice of parallel programming","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":26,"referenced_works":["https://openalex.org/W176746981","https://openalex.org/W1542975293","https://openalex.org/W1850380174","https://openalex.org/W1963520590","https://openalex.org/W1986913310","https://openalex.org/W1994163561","https://openalex.org/W2044925098","https://openalex.org/W2054961017","https://openalex.org/W2060499019","https://openalex.org/W2079854797","https://openalex.org/W2094222793","https://openalex.org/W2108204150","https://openalex.org/W2113751407","https://openalex.org/W2116145395","https://openalex.org/W2119653453","https://openalex.org/W2126501440","https://openalex.org/W2134631561","https://openalex.org/W2149473197","https://openalex.org/W2150871235","https://openalex.org/W2152885346","https://openalex.org/W2152988224","https://openalex.org/W2167710134","https://openalex.org/W2171146288","https://openalex.org/W2340530615","https://openalex.org/W2955325419","https://openalex.org/W3212830316"],"related_works":["https://openalex.org/W1489494763","https://openalex.org/W2045742725","https://openalex.org/W2046858187","https://openalex.org/W2117242058","https://openalex.org/W2979476749","https://openalex.org/W2048419619","https://openalex.org/W4247918562","https://openalex.org/W1538734857","https://openalex.org/W2132511067","https://openalex.org/W2040204382"],"abstract_inverted_index":{"We":[0],"present":[1],"the":[2],"programming":[3],"model,":[4],"design":[5],"and":[6],"implementation":[7],"of":[8,27],"NePalTM;":[9],"a":[10],"transactional":[11],"memory":[12],"system":[13],"where":[14],"atomic":[15],"blocks":[16],"can":[17],"be":[18],"used":[19],"for":[20],"concurrency":[21],"control":[22],"at":[23],"an":[24],"arbitrary":[25],"level":[26],"nested":[28],"parallelism.":[29]},"counts_by_year":[{"year":2025,"cited_by_count":1},{"year":2024,"cited_by_count":1},{"year":2021,"cited_by_count":1},{"year":2020,"cited_by_count":2},{"year":2017,"cited_by_count":1},{"year":2014,"cited_by_count":2},{"year":2013,"cited_by_count":4},{"year":2012,"cited_by_count":2}],"updated_date":"2026-06-11T09:08:48.828518","created_date":"2016-06-24T00:00:00"}