{"id":"https://openalex.org/W1993374007","doi":"https://doi.org/10.1145/1499799.1499904","title":"A parallel processor for evaluation studies","display_name":"A parallel processor for evaluation studies","publication_year":1976,"publication_date":"1976-01-01","ids":{"openalex":"https://openalex.org/W1993374007","doi":"https://doi.org/10.1145/1499799.1499904","mag":"1993374007"},"language":"en","primary_location":{"id":"doi:10.1145/1499799.1499904","is_oa":false,"landing_page_url":"https://doi.org/10.1145/1499799.1499904","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the June 7-10, 1976, national computer conference and exposition on - AFIPS '76","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5112712305","display_name":"Gary J Nutt","orcid":null},"institutions":[{"id":"https://openalex.org/I188538660","display_name":"University of Colorado Boulder","ror":"https://ror.org/02ttsq026","country_code":"US","type":"education","lineage":["https://openalex.org/I188538660"]},{"id":"https://openalex.org/I2802236040","display_name":"University of Colorado System","ror":"https://ror.org/00jc20583","country_code":"US","type":"education","lineage":["https://openalex.org/I2802236040"]}],"countries":["US"],"is_corresponding":true,"raw_author_name":"Gary J. Nutt","raw_affiliation_strings":["University of Colorado, Boulder, Colorado"],"affiliations":[{"raw_affiliation_string":"University of Colorado, Boulder, Colorado","institution_ids":["https://openalex.org/I2802236040","https://openalex.org/I188538660"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":1,"corresponding_author_ids":["https://openalex.org/A5112712305"],"corresponding_institution_ids":["https://openalex.org/I188538660","https://openalex.org/I2802236040"],"apc_list":null,"apc_paid":null,"fwci":3.4658,"has_fulltext":false,"cited_by_count":5,"citation_normalized_percentile":{"value":0.90720391,"is_in_top_1_percent":false,"is_in_top_10_percent":true},"cited_by_percentile_year":null,"biblio":{"volume":null,"issue":null,"first_page":"769","last_page":"769"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9994999766349792,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.9993000030517578,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.8508745431900024},{"id":"https://openalex.org/keywords/parallelism","display_name":"Parallelism (grammar)","score":0.6974435448646545},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.6592879891395569},{"id":"https://openalex.org/keywords/instruction-level-parallelism","display_name":"Instruction-level parallelism","score":0.6295417547225952},{"id":"https://openalex.org/keywords/associative-property","display_name":"Associative property","score":0.5855564475059509},{"id":"https://openalex.org/keywords/data-parallelism","display_name":"Data parallelism","score":0.5707967877388},{"id":"https://openalex.org/keywords/cellular-architecture","display_name":"Cellular architecture","score":0.5144667625427246},{"id":"https://openalex.org/keywords/task-parallelism","display_name":"Task parallelism","score":0.5047143697738647},{"id":"https://openalex.org/keywords/architecture","display_name":"Architecture","score":0.5037843585014343},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.45134609937667847},{"id":"https://openalex.org/keywords/control-unit","display_name":"Control unit","score":0.41516441106796265},{"id":"https://openalex.org/keywords/reference-architecture","display_name":"Reference architecture","score":0.21749165654182434},{"id":"https://openalex.org/keywords/programming-language","display_name":"Programming language","score":0.17458847165107727},{"id":"https://openalex.org/keywords/software-architecture","display_name":"Software architecture","score":0.11950051784515381},{"id":"https://openalex.org/keywords/software","display_name":"Software","score":0.08148789405822754}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.8508745431900024},{"id":"https://openalex.org/C2781172179","wikidata":"https://www.wikidata.org/wiki/Q853109","display_name":"Parallelism (grammar)","level":2,"score":0.6974435448646545},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.6592879891395569},{"id":"https://openalex.org/C140763907","wikidata":"https://www.wikidata.org/wiki/Q2714055","display_name":"Instruction-level parallelism","level":3,"score":0.6295417547225952},{"id":"https://openalex.org/C159423971","wikidata":"https://www.wikidata.org/wiki/Q177251","display_name":"Associative property","level":2,"score":0.5855564475059509},{"id":"https://openalex.org/C61483411","wikidata":"https://www.wikidata.org/wiki/Q3124522","display_name":"Data parallelism","level":3,"score":0.5707967877388},{"id":"https://openalex.org/C37139622","wikidata":"https://www.wikidata.org/wiki/Q386953","display_name":"Cellular architecture","level":5,"score":0.5144667625427246},{"id":"https://openalex.org/C42992933","wikidata":"https://www.wikidata.org/wiki/Q691169","display_name":"Task parallelism","level":3,"score":0.5047143697738647},{"id":"https://openalex.org/C123657996","wikidata":"https://www.wikidata.org/wiki/Q12271","display_name":"Architecture","level":2,"score":0.5037843585014343},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.45134609937667847},{"id":"https://openalex.org/C81988521","wikidata":"https://www.wikidata.org/wiki/Q676838","display_name":"Control unit","level":2,"score":0.41516441106796265},{"id":"https://openalex.org/C55356503","wikidata":"https://www.wikidata.org/wiki/Q2136675","display_name":"Reference architecture","level":4,"score":0.21749165654182434},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.17458847165107727},{"id":"https://openalex.org/C35869016","wikidata":"https://www.wikidata.org/wiki/Q846636","display_name":"Software architecture","level":3,"score":0.11950051784515381},{"id":"https://openalex.org/C2777904410","wikidata":"https://www.wikidata.org/wiki/Q7397","display_name":"Software","level":2,"score":0.08148789405822754},{"id":"https://openalex.org/C153349607","wikidata":"https://www.wikidata.org/wiki/Q36649","display_name":"Visual arts","level":1,"score":0.0},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.0},{"id":"https://openalex.org/C142362112","wikidata":"https://www.wikidata.org/wiki/Q735","display_name":"Art","level":0,"score":0.0},{"id":"https://openalex.org/C202444582","wikidata":"https://www.wikidata.org/wiki/Q837863","display_name":"Pure mathematics","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1145/1499799.1499904","is_oa":false,"landing_page_url":"https://doi.org/10.1145/1499799.1499904","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the June 7-10, 1976, national computer conference and exposition on - AFIPS '76","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":10,"referenced_works":["https://openalex.org/W1979826115","https://openalex.org/W1986280831","https://openalex.org/W1995459446","https://openalex.org/W2013259664","https://openalex.org/W2017206111","https://openalex.org/W2039804807","https://openalex.org/W2073407440","https://openalex.org/W2078315796","https://openalex.org/W2094969361","https://openalex.org/W2123509893"],"related_works":["https://openalex.org/W4240606930","https://openalex.org/W2526302199","https://openalex.org/W2003935582","https://openalex.org/W2950520577","https://openalex.org/W3007272028","https://openalex.org/W2040503315","https://openalex.org/W1501159154","https://openalex.org/W2009213655","https://openalex.org/W2468095077","https://openalex.org/W168408236"],"abstract_inverted_index":{"The":[0,23,55],"Multi":[1],"Associative":[2],"Processor":[3],"system":[4],"is":[5,33,46,60,69],"a":[6,15],"multiple":[7],"control":[8],"unit":[9],"parallel":[10],"processor":[11],"capable":[12],"of":[13,17,39,57,74,77],"executing":[14],"maximum":[16],"8":[18],"single-instruction-stream,":[19],"multiple-data-stream":[20],"programs":[21],"simultaneously.":[22],"architecture":[24,56],"supports":[25],"parallelism":[26,37,51],"at":[27],"two":[28],"levels:":[29],"the":[30,34,43,47,58,67,75,78,85],"lower":[31],"level":[32,45],"tightly":[35],"coupled":[36,50],"typical":[38],"array":[40],"processors,":[41],"and":[42,62,81],"higher":[44],"more":[48],"loosely":[49],"between":[52],"independent":[53],"processes.":[54],"machine":[59,68,86],"described":[61],"an":[63],"example":[64],"program":[65],"for":[66],"given":[70],"to":[71],"illustrate":[72],"many":[73],"concepts":[76],"architecture.":[79],"Measurement":[80],"evaluation":[82],"studies":[83],"on":[84],"are":[87],"also":[88],"briefly":[89],"discussed.":[90]},"counts_by_year":[],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}