{"id":"https://openalex.org/W1969957162","doi":"https://doi.org/10.1145/1499799.1499890","title":"The CMU RT-CAD system","display_name":"The CMU RT-CAD system","publication_year":1976,"publication_date":"1976-01-01","ids":{"openalex":"https://openalex.org/W1969957162","doi":"https://doi.org/10.1145/1499799.1499890","mag":"1969957162"},"language":"en","primary_location":{"id":"doi:10.1145/1499799.1499890","is_oa":false,"landing_page_url":"https://doi.org/10.1145/1499799.1499890","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the June 7-10, 1976, national computer conference and exposition on - AFIPS '76","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5024012980","display_name":"Daniel P. Siewiorek","orcid":"https://orcid.org/0000-0001-6644-3929"},"institutions":[{"id":"https://openalex.org/I74973139","display_name":"Carnegie Mellon University","ror":"https://ror.org/05x2bcf33","country_code":"US","type":"education","lineage":["https://openalex.org/I74973139"]}],"countries":["US"],"is_corresponding":true,"raw_author_name":"Daniel P. Siewiorek","raw_affiliation_strings":["Carnegie-Mellon University, Pittsburgh, Pennsylvania","Carnegie Mellon Univ, Pittsburgh, Pennsylvania#TAB#"],"affiliations":[{"raw_affiliation_string":"Carnegie-Mellon University, Pittsburgh, Pennsylvania","institution_ids":["https://openalex.org/I74973139"]},{"raw_affiliation_string":"Carnegie Mellon Univ, Pittsburgh, Pennsylvania#TAB#","institution_ids":["https://openalex.org/I74973139"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5057169236","display_name":"Mario R. Barbacci","orcid":null},"institutions":[{"id":"https://openalex.org/I74973139","display_name":"Carnegie Mellon University","ror":"https://ror.org/05x2bcf33","country_code":"US","type":"education","lineage":["https://openalex.org/I74973139"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Mario R. Barbacci","raw_affiliation_strings":["Carnegie-Mellon University, Pittsburgh, Pennsylvania","Carnegie Mellon Univ, Pittsburgh, Pennsylvania#TAB#"],"affiliations":[{"raw_affiliation_string":"Carnegie-Mellon University, Pittsburgh, Pennsylvania","institution_ids":["https://openalex.org/I74973139"]},{"raw_affiliation_string":"Carnegie Mellon Univ, Pittsburgh, Pennsylvania#TAB#","institution_ids":["https://openalex.org/I74973139"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":2,"corresponding_author_ids":["https://openalex.org/A5024012980"],"corresponding_institution_ids":["https://openalex.org/I74973139"],"apc_list":null,"apc_paid":null,"fwci":5.7998,"has_fulltext":false,"cited_by_count":32,"citation_normalized_percentile":{"value":0.95818815,"is_in_top_1_percent":false,"is_in_top_10_percent":true},"cited_by_percentile_year":{"min":94,"max":96},"biblio":{"volume":null,"issue":null,"first_page":"643","last_page":"643"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9966999888420105,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9966999888420105,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9955999851226807,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11527","display_name":"3D IC and TSV technologies","score":0.9883999824523926,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7049399018287659},{"id":"https://openalex.org/keywords/register-transfer-level","display_name":"Register-transfer level","score":0.5013656616210938},{"id":"https://openalex.org/keywords/component","display_name":"Component (thermodynamics)","score":0.4931437373161316},{"id":"https://openalex.org/keywords/shift-register","display_name":"Shift register","score":0.4456167221069336},{"id":"https://openalex.org/keywords/scale","display_name":"Scale (ratio)","score":0.43184414505958557},{"id":"https://openalex.org/keywords/logic-synthesis","display_name":"Logic synthesis","score":0.41707509756088257},{"id":"https://openalex.org/keywords/digital-electronics","display_name":"Digital electronics","score":0.41305306553840637},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.4066624641418457},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.3927277624607086},{"id":"https://openalex.org/keywords/logic-gate","display_name":"Logic gate","score":0.3689475357532501},{"id":"https://openalex.org/keywords/arithmetic","display_name":"Arithmetic","score":0.3444318175315857},{"id":"https://openalex.org/keywords/electronic-circuit","display_name":"Electronic circuit","score":0.21781578660011292},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.19101151823997498},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.1452181041240692},{"id":"https://openalex.org/keywords/telecommunications","display_name":"Telecommunications","score":0.1403719186782837},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.08290475606918335},{"id":"https://openalex.org/keywords/mathematics","display_name":"Mathematics","score":0.07496309280395508}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7049399018287659},{"id":"https://openalex.org/C34854456","wikidata":"https://www.wikidata.org/wiki/Q1484552","display_name":"Register-transfer level","level":4,"score":0.5013656616210938},{"id":"https://openalex.org/C168167062","wikidata":"https://www.wikidata.org/wiki/Q1117970","display_name":"Component (thermodynamics)","level":2,"score":0.4931437373161316},{"id":"https://openalex.org/C49654631","wikidata":"https://www.wikidata.org/wiki/Q746165","display_name":"Shift register","level":3,"score":0.4456167221069336},{"id":"https://openalex.org/C2778755073","wikidata":"https://www.wikidata.org/wiki/Q10858537","display_name":"Scale (ratio)","level":2,"score":0.43184414505958557},{"id":"https://openalex.org/C157922185","wikidata":"https://www.wikidata.org/wiki/Q173198","display_name":"Logic synthesis","level":3,"score":0.41707509756088257},{"id":"https://openalex.org/C81843906","wikidata":"https://www.wikidata.org/wiki/Q173156","display_name":"Digital electronics","level":3,"score":0.41305306553840637},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.4066624641418457},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.3927277624607086},{"id":"https://openalex.org/C131017901","wikidata":"https://www.wikidata.org/wiki/Q170451","display_name":"Logic gate","level":2,"score":0.3689475357532501},{"id":"https://openalex.org/C94375191","wikidata":"https://www.wikidata.org/wiki/Q11205","display_name":"Arithmetic","level":1,"score":0.3444318175315857},{"id":"https://openalex.org/C134146338","wikidata":"https://www.wikidata.org/wiki/Q1815901","display_name":"Electronic circuit","level":2,"score":0.21781578660011292},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.19101151823997498},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.1452181041240692},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.1403719186782837},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.08290475606918335},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.07496309280395508},{"id":"https://openalex.org/C97355855","wikidata":"https://www.wikidata.org/wiki/Q11473","display_name":"Thermodynamics","level":1,"score":0.0},{"id":"https://openalex.org/C62520636","wikidata":"https://www.wikidata.org/wiki/Q944","display_name":"Quantum mechanics","level":1,"score":0.0},{"id":"https://openalex.org/C121332964","wikidata":"https://www.wikidata.org/wiki/Q413","display_name":"Physics","level":0,"score":0.0},{"id":"https://openalex.org/C165005293","wikidata":"https://www.wikidata.org/wiki/Q1074500","display_name":"Chip","level":2,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1145/1499799.1499890","is_oa":false,"landing_page_url":"https://doi.org/10.1145/1499799.1499890","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the June 7-10, 1976, national computer conference and exposition on - AFIPS '76","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"display_name":"Affordable and clean energy","score":0.5199999809265137,"id":"https://metadata.un.org/sdg/7"}],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":9,"referenced_works":["https://openalex.org/W15961474","https://openalex.org/W225746166","https://openalex.org/W1664574281","https://openalex.org/W1992700801","https://openalex.org/W2003328979","https://openalex.org/W2025642196","https://openalex.org/W2051994456","https://openalex.org/W2054114280","https://openalex.org/W2086285232"],"related_works":["https://openalex.org/W2098419840","https://openalex.org/W2351310008","https://openalex.org/W2377041390","https://openalex.org/W2386022279","https://openalex.org/W659242671","https://openalex.org/W2766377030","https://openalex.org/W2243536805","https://openalex.org/W2181841040","https://openalex.org/W2462231960","https://openalex.org/W2913530739"],"abstract_inverted_index":{"As":[0],"technology":[1],"has":[2,80],"evolved":[3],"the":[4,19,53,112],"primitive":[5,86,103],"components":[6,27,63,87,104,118],"available":[7,45],"to":[8,106,120],"a":[9],"digital":[10],"system":[11],"designer":[12,20],"have":[13],"changed":[14],"dramatically.":[15],"Twenty-five":[16],"years":[17],"ago":[18],"constructed":[21],"systems":[22,90],"out":[23],"of":[24,55,75,114,116],"circuit":[25,35],"level":[26,36,62],"such":[28],"as":[29,38,46],"resistors":[30],"and":[31,42,66,83,110],"diodes.":[32],"Subsequently":[33],"switching":[34],"components,":[37],"represented":[39],"by":[40],"gates":[41],"flip-flops,":[43],"became":[44],"small":[47],"scale":[48,57,77],"integration":[49,58,78],"(SSI)":[50],"components.":[51],"With":[52],"introduction":[54,115],"medium":[56],"(MSI)":[59],"register":[60],"transfer":[61],"appeared:":[64],"arithmetic":[65],"logic":[67],"units,":[68],"registers,":[69,71],"shift":[70],"etc.":[72],"The":[73],"advent":[74],"large":[76],"(LSI)":[79],"made":[81],"memories":[82],"even":[84],"processors":[85],"from":[88,98],"which":[89],"are":[91],"designed.":[92],"Two":[93],"trends":[94],"can":[95],"be":[96],"observed":[97],"this":[99],"technological":[100],"evolution:":[101],"(1)":[102],"continue":[105],"increase":[107],"in":[108],"complexity":[109],"(2)":[111],"rate":[113],"new":[117],"continues":[119],"increase.":[121]},"counts_by_year":[{"year":2018,"cited_by_count":2}],"updated_date":"2026-03-10T16:38:18.471706","created_date":"2025-10-10T00:00:00"}
