{"id":"https://openalex.org/W2051874670","doi":"https://doi.org/10.1145/1497561.1497564","title":"Instrumenting AMS assertion verification on commercial platforms","display_name":"Instrumenting AMS assertion verification on commercial platforms","publication_year":2009,"publication_date":"2009-03-01","ids":{"openalex":"https://openalex.org/W2051874670","doi":"https://doi.org/10.1145/1497561.1497564","mag":"2051874670"},"language":"en","primary_location":{"id":"doi:10.1145/1497561.1497564","is_oa":false,"landing_page_url":"https://doi.org/10.1145/1497561.1497564","pdf_url":null,"source":{"id":"https://openalex.org/S105046310","display_name":"ACM Transactions on Design Automation of Electronic Systems","issn_l":"1084-4309","issn":["1084-4309","1557-7309"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319798","host_organization_name":"Association for Computing Machinery","host_organization_lineage":["https://openalex.org/P4310319798"],"host_organization_lineage_names":["Association for Computing Machinery"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"ACM Transactions on Design Automation of Electronic Systems","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5023238582","display_name":"Rajdeep Mukhopadhyay","orcid":null},"institutions":[{"id":"https://openalex.org/I145894827","display_name":"Indian Institute of Technology Kharagpur","ror":"https://ror.org/03w5sq511","country_code":"IN","type":"education","lineage":["https://openalex.org/I145894827"]}],"countries":["IN"],"is_corresponding":false,"raw_author_name":"Rajdeep Mukhopadhyay","raw_affiliation_strings":["IIT Kharagpur, India"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"IIT Kharagpur, India","institution_ids":["https://openalex.org/I145894827"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5052994118","display_name":"S.K. Panda","orcid":"https://orcid.org/0000-0001-8876-909X"},"institutions":[{"id":"https://openalex.org/I145894827","display_name":"Indian Institute of Technology Kharagpur","ror":"https://ror.org/03w5sq511","country_code":"IN","type":"education","lineage":["https://openalex.org/I145894827"]}],"countries":["IN"],"is_corresponding":false,"raw_author_name":"S. K. Panda","raw_affiliation_strings":["IIT Kharagpur, India"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"IIT Kharagpur, India","institution_ids":["https://openalex.org/I145894827"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5033329960","display_name":"Pallab Dasgupta","orcid":"https://orcid.org/0000-0002-2178-8154"},"institutions":[{"id":"https://openalex.org/I145894827","display_name":"Indian Institute of Technology Kharagpur","ror":"https://ror.org/03w5sq511","country_code":"IN","type":"education","lineage":["https://openalex.org/I145894827"]}],"countries":["IN"],"is_corresponding":false,"raw_author_name":"Pallab Dasgupta","raw_affiliation_strings":["IIT Kharagpur, India"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"IIT Kharagpur, India","institution_ids":["https://openalex.org/I145894827"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5070344609","display_name":"John Gough","orcid":null},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"John Gough","raw_affiliation_strings":["National Semiconductor Corp., Greenock, UK"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"National Semiconductor Corp., Greenock, UK","institution_ids":[]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":4,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":5.318,"has_fulltext":false,"cited_by_count":28,"citation_normalized_percentile":{"value":0.95914449,"is_in_top_1_percent":false,"is_in_top_10_percent":true},"cited_by_percentile_year":{"min":89,"max":99},"biblio":{"volume":"14","issue":"2","first_page":"1","last_page":"47"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10142","display_name":"Formal Methods in Verification","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/1703","display_name":"Computational Theory and Mathematics"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10142","display_name":"Formal Methods in Verification","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/1703","display_name":"Computational Theory and Mathematics"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9994000196456909,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11005","display_name":"Radiation Effects in Electronics","score":0.9994000196456909,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.874360203742981},{"id":"https://openalex.org/keywords/debugging","display_name":"Debugging","score":0.7215294241905212},{"id":"https://openalex.org/keywords/assertion","display_name":"Assertion","score":0.6942305564880371},{"id":"https://openalex.org/keywords/functional-verification","display_name":"Functional verification","score":0.6616891026496887},{"id":"https://openalex.org/keywords/verilog","display_name":"Verilog","score":0.6506261825561523},{"id":"https://openalex.org/keywords/cadence","display_name":"Cadence","score":0.5849694013595581},{"id":"https://openalex.org/keywords/formal-verification","display_name":"Formal verification","score":0.537761390209198},{"id":"https://openalex.org/keywords/domain","display_name":"Domain (mathematical analysis)","score":0.5197569727897644},{"id":"https://openalex.org/keywords/intelligent-verification","display_name":"Intelligent verification","score":0.5152642726898193},{"id":"https://openalex.org/keywords/runtime-verification","display_name":"Runtime verification","score":0.4118630588054657},{"id":"https://openalex.org/keywords/software-engineering","display_name":"Software engineering","score":0.3954218626022339},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.39406818151474},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.3757377862930298},{"id":"https://openalex.org/keywords/programming-language","display_name":"Programming language","score":0.30021560192108154},{"id":"https://openalex.org/keywords/software","display_name":"Software","score":0.14253804087638855},{"id":"https://openalex.org/keywords/software-development","display_name":"Software development","score":0.0904206931591034},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.08040890097618103}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.874360203742981},{"id":"https://openalex.org/C168065819","wikidata":"https://www.wikidata.org/wiki/Q845566","display_name":"Debugging","level":2,"score":0.7215294241905212},{"id":"https://openalex.org/C40422974","wikidata":"https://www.wikidata.org/wiki/Q741248","display_name":"Assertion","level":2,"score":0.6942305564880371},{"id":"https://openalex.org/C62460635","wikidata":"https://www.wikidata.org/wiki/Q5508853","display_name":"Functional verification","level":3,"score":0.6616891026496887},{"id":"https://openalex.org/C2779030575","wikidata":"https://www.wikidata.org/wiki/Q827773","display_name":"Verilog","level":3,"score":0.6506261825561523},{"id":"https://openalex.org/C2777125575","wikidata":"https://www.wikidata.org/wiki/Q14088448","display_name":"Cadence","level":2,"score":0.5849694013595581},{"id":"https://openalex.org/C111498074","wikidata":"https://www.wikidata.org/wiki/Q173326","display_name":"Formal verification","level":2,"score":0.537761390209198},{"id":"https://openalex.org/C36503486","wikidata":"https://www.wikidata.org/wiki/Q11235244","display_name":"Domain (mathematical analysis)","level":2,"score":0.5197569727897644},{"id":"https://openalex.org/C3406870","wikidata":"https://www.wikidata.org/wiki/Q6044160","display_name":"Intelligent verification","level":5,"score":0.5152642726898193},{"id":"https://openalex.org/C202973057","wikidata":"https://www.wikidata.org/wiki/Q7380130","display_name":"Runtime verification","level":3,"score":0.4118630588054657},{"id":"https://openalex.org/C115903868","wikidata":"https://www.wikidata.org/wiki/Q80993","display_name":"Software engineering","level":1,"score":0.3954218626022339},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.39406818151474},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.3757377862930298},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.30021560192108154},{"id":"https://openalex.org/C2777904410","wikidata":"https://www.wikidata.org/wiki/Q7397","display_name":"Software","level":2,"score":0.14253804087638855},{"id":"https://openalex.org/C529173508","wikidata":"https://www.wikidata.org/wiki/Q638608","display_name":"Software development","level":3,"score":0.0904206931591034},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.08040890097618103},{"id":"https://openalex.org/C186846655","wikidata":"https://www.wikidata.org/wiki/Q3398377","display_name":"Software construction","level":4,"score":0.0},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.0},{"id":"https://openalex.org/C134306372","wikidata":"https://www.wikidata.org/wiki/Q7754","display_name":"Mathematical analysis","level":1,"score":0.0},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.0},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1145/1497561.1497564","is_oa":false,"landing_page_url":"https://doi.org/10.1145/1497561.1497564","pdf_url":null,"source":{"id":"https://openalex.org/S105046310","display_name":"ACM Transactions on Design Automation of Electronic Systems","issn_l":"1084-4309","issn":["1084-4309","1557-7309"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319798","host_organization_name":"Association for Computing Machinery","host_organization_lineage":["https://openalex.org/P4310319798"],"host_organization_lineage_names":["Association for Computing Machinery"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"ACM Transactions on Design Automation of Electronic Systems","raw_type":"journal-article"}],"best_oa_location":null,"sustainable_development_goals":[{"display_name":"Industry, innovation and infrastructure","score":0.6200000047683716,"id":"https://metadata.un.org/sdg/9"}],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":33,"referenced_works":["https://openalex.org/W37827039","https://openalex.org/W77078696","https://openalex.org/W566385658","https://openalex.org/W935054506","https://openalex.org/W1480537711","https://openalex.org/W1483606732","https://openalex.org/W1494737186","https://openalex.org/W1522694098","https://openalex.org/W1537946603","https://openalex.org/W1542641677","https://openalex.org/W1547304883","https://openalex.org/W1568322431","https://openalex.org/W1570732927","https://openalex.org/W1576278728","https://openalex.org/W2004463571","https://openalex.org/W2049696538","https://openalex.org/W2058326882","https://openalex.org/W2060095702","https://openalex.org/W2097451232","https://openalex.org/W2104439088","https://openalex.org/W2104643771","https://openalex.org/W2106026059","https://openalex.org/W2117350447","https://openalex.org/W2125967324","https://openalex.org/W2138839649","https://openalex.org/W2146806823","https://openalex.org/W2156581962","https://openalex.org/W2540677422","https://openalex.org/W2561675875","https://openalex.org/W2914931491","https://openalex.org/W4243298546","https://openalex.org/W4250395788","https://openalex.org/W4256745561"],"related_works":["https://openalex.org/W3036403349","https://openalex.org/W2035244079","https://openalex.org/W2392047570","https://openalex.org/W4301348901","https://openalex.org/W4205300843","https://openalex.org/W2350806125","https://openalex.org/W2325633191","https://openalex.org/W2391022620","https://openalex.org/W2361469993","https://openalex.org/W4375853833"],"abstract_inverted_index":{"The":[0,76],"industry":[1],"trend":[2],"appears":[3],"to":[4,34,99,120],"be":[5,35,245],"moving":[6],"towards":[7],"designs":[8],"that":[9,32,58,159,167,214],"integrate":[10],"large":[11,25],"digital":[12],"circuits":[13],"with":[14,63,240],"multiple":[15],"analog/RF":[16],"(radio":[17],"frequency)":[18],"interfaces.":[19],"In":[20,105],"the":[21,28,42,49,73,112,115,121,134,148,153,175,193,199,216,229],"verification":[22,91,102,131,200],"of":[23,30,129,150,177,185,195,201,218,232,246],"these":[24],"integrated":[26,204],"circuits,":[27],"number":[29],"nets":[31],"need":[33,50],"monitored":[36],"has":[37,46],"been":[38,47],"growing":[39],"rapidly.":[40],"Consequently,":[41],"mixed-signal":[43],"design":[44,74],"community":[45],"feeling":[48],"for":[51,180,225],"AMS":[52,86,90,122,130,226],"(Analog":[53],"and":[54,67,93,170,188,236,248],"Mixed":[55],"Signal)":[56],"assertions":[57],"can":[59,162],"automatically":[60],"monitor":[61],"conformance":[62],"expected":[64],"time-domain":[65],"behavior":[66],"help":[68],"in":[69,79,164,215],"debugging":[70],"deviations":[71],"from":[72,209],"intent.":[75],"main":[77],"challenges":[78],"providing":[80],"this":[81,106],"support":[82,100,179],"are":[83],"(a)":[84],"developing":[85],"assertion":[87,101,227],"languages":[88],"or":[89],"libraries,":[92],"(b)":[94],"instrumenting":[95],"existing":[96,219,241],"commercial":[97,242],"simulators":[98,243],"during":[103],"simulation.":[104],"article,":[107],"we":[108],"report":[109,174],"two":[110],"approaches:":[111],"first":[113],"extends":[114,136],"Open":[116],"Verification":[117],"Library":[118],"(OVL)":[119],"domain":[123],"by":[124,140],"integrating":[125,233],"a":[126,183],"new":[127],"collection":[128],"libraries;":[132],"while":[133,157],"second":[135],"SystemVerilog":[137],"Assertions":[138],"(SVA)":[139],"augmenting":[141],"analog":[142],"predicates":[143],"into":[144],"SVA.":[145],"We":[146,172,191,212],"demonstrate":[147,192],"use":[149],"AMS-OVL":[151],"on":[152,198],"Cadence":[154,186],"Virtuoso":[155],"environment":[156,166],"emphasizing":[158],"our":[160,234,237],"libraries":[161,235],"work":[163],"any":[165],"supports":[168],"Verilog":[169],"Verilog-A.":[171],"also":[173],"development":[176],"tool":[178,238],"AMS-SVA":[181],"using":[182],"combination":[184],"NCSIM":[187],"Synopsys":[189],"VCS.":[190],"utility":[194],"both":[196],"approaches":[197,231],"LP3918,":[202],"an":[203],"power":[205],"management":[206],"unit":[207],"(PMU)":[208],"National":[210],"Semiconductors.":[211],"believe":[213],"absence":[217],"EDA":[220],"(Electronic":[221],"Design":[222],"Automation)":[223],"tools":[224],"verification,":[228],"proposed":[230],"sets":[239],"will":[244],"considerable":[247],"immediate":[249],"practical":[250],"value.":[251]},"counts_by_year":[{"year":2022,"cited_by_count":1},{"year":2021,"cited_by_count":1},{"year":2020,"cited_by_count":2},{"year":2018,"cited_by_count":1},{"year":2016,"cited_by_count":2},{"year":2015,"cited_by_count":1},{"year":2014,"cited_by_count":3},{"year":2013,"cited_by_count":2},{"year":2012,"cited_by_count":6}],"updated_date":"2026-06-11T09:08:48.828518","created_date":"2025-10-10T00:00:00"}
