{"id":"https://openalex.org/W2160996172","doi":"https://doi.org/10.1145/1454115.1454145","title":"Adaptive insertion policies for managing shared caches","display_name":"Adaptive insertion policies for managing shared caches","publication_year":2008,"publication_date":"2008-10-25","ids":{"openalex":"https://openalex.org/W2160996172","doi":"https://doi.org/10.1145/1454115.1454145","mag":"2160996172"},"language":"en","primary_location":{"id":"doi:10.1145/1454115.1454145","is_oa":false,"landing_page_url":"https://doi.org/10.1145/1454115.1454145","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 17th international conference on Parallel architectures and compilation techniques","raw_type":"proceedings-article"},"type":"conference-paper","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5078825915","display_name":"Aamer Jaleel","orcid":"https://orcid.org/0000-0002-5709-2992"},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Aamer Jaleel","raw_affiliation_strings":["Intel Corporation, Hudson, MA, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Intel Corporation, Hudson, MA, USA","institution_ids":["https://openalex.org/I1343180700"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5084297749","display_name":"William Hasenplaugh","orcid":null},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"William Hasenplaugh","raw_affiliation_strings":["Intel Corporation, Hudson, MA, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Intel Corporation, Hudson, MA, USA","institution_ids":["https://openalex.org/I1343180700"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5082772077","display_name":"Moinuddin K. Qureshi","orcid":"https://orcid.org/0000-0002-1314-9096"},"institutions":[{"id":"https://openalex.org/I4210114115","display_name":"IBM Research - Thomas J. Watson Research Center","ror":"https://ror.org/0265w5591","country_code":"US","type":"facility","lineage":["https://openalex.org/I1341412227","https://openalex.org/I4210114115"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Moinuddin Qureshi","raw_affiliation_strings":["IBM T. J. Watson Research Center, Yorktown Heights, NY, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"IBM T. J. Watson Research Center, Yorktown Heights, NY, USA","institution_ids":["https://openalex.org/I4210114115"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5031399500","display_name":"Julien S\u00e9bot","orcid":null},"institutions":[{"id":"https://openalex.org/I4210104622","display_name":"Intel (Israel)","ror":"https://ror.org/027t2s119","country_code":"IL","type":"company","lineage":["https://openalex.org/I1343180700","https://openalex.org/I4210104622"]}],"countries":["IL"],"is_corresponding":false,"raw_author_name":"Julien Sebot","raw_affiliation_strings":["Intel Israel Design Center, Haifa, Israel"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Intel Israel Design Center, Haifa, Israel","institution_ids":["https://openalex.org/I4210104622"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5048387429","display_name":"Simon C. Steely","orcid":null},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Simon Steely","raw_affiliation_strings":["Intel Corporation, Hudson, MA, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Intel Corporation, Hudson, MA, USA","institution_ids":["https://openalex.org/I1343180700"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5024384625","display_name":"Joel Emer","orcid":null},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Joel Emer","raw_affiliation_strings":["Intel Corporation, Hudson, MA, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Intel Corporation, Hudson, MA, USA","institution_ids":["https://openalex.org/I1343180700"]}]}],"institutions":[],"countries_distinct_count":2,"institutions_distinct_count":3,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":null,"has_fulltext":false,"cited_by_count":300,"citation_normalized_percentile":null,"cited_by_percentile_year":null,"biblio":{"volume":null,"issue":null,"first_page":"208","last_page":"219"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.9994000196456909,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10715","display_name":"Distributed and Parallel Computing Systems","score":0.9991000294685364,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.8404685258865356},{"id":"https://openalex.org/keywords/cache","display_name":"Cache","score":0.8150466680526733},{"id":"https://openalex.org/keywords/cache-algorithms","display_name":"Cache algorithms","score":0.7067139148712158},{"id":"https://openalex.org/keywords/cache-pollution","display_name":"Cache pollution","score":0.6955481171607971},{"id":"https://openalex.org/keywords/bus-sniffing","display_name":"Bus sniffing","score":0.663468599319458},{"id":"https://openalex.org/keywords/cache-invalidation","display_name":"Cache invalidation","score":0.6429199576377869},{"id":"https://openalex.org/keywords/smart-cache","display_name":"Smart Cache","score":0.6045514345169067},{"id":"https://openalex.org/keywords/cache-coloring","display_name":"Cache coloring","score":0.5933575630187988},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.5810714364051819},{"id":"https://openalex.org/keywords/working-set","display_name":"Working set","score":0.5141106247901917},{"id":"https://openalex.org/keywords/page-cache","display_name":"Page cache","score":0.513494074344635},{"id":"https://openalex.org/keywords/shared-memory","display_name":"Shared memory","score":0.4768185019493103},{"id":"https://openalex.org/keywords/set","display_name":"Set (abstract data type)","score":0.4563307464122772},{"id":"https://openalex.org/keywords/cache-coherence","display_name":"Cache coherence","score":0.4205091893672943},{"id":"https://openalex.org/keywords/cpu-cache","display_name":"CPU cache","score":0.3973340094089508},{"id":"https://openalex.org/keywords/operating-system","display_name":"Operating system","score":0.34083306789398193},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.3351007103919983},{"id":"https://openalex.org/keywords/programming-language","display_name":"Programming language","score":0.06199616193771362}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.8404685258865356},{"id":"https://openalex.org/C115537543","wikidata":"https://www.wikidata.org/wiki/Q165596","display_name":"Cache","level":2,"score":0.8150466680526733},{"id":"https://openalex.org/C38556500","wikidata":"https://www.wikidata.org/wiki/Q13404475","display_name":"Cache algorithms","level":4,"score":0.7067139148712158},{"id":"https://openalex.org/C113166858","wikidata":"https://www.wikidata.org/wiki/Q5015981","display_name":"Cache pollution","level":5,"score":0.6955481171607971},{"id":"https://openalex.org/C51185590","wikidata":"https://www.wikidata.org/wiki/Q1017228","display_name":"Bus sniffing","level":5,"score":0.663468599319458},{"id":"https://openalex.org/C25536678","wikidata":"https://www.wikidata.org/wiki/Q5015977","display_name":"Cache invalidation","level":5,"score":0.6429199576377869},{"id":"https://openalex.org/C167713795","wikidata":"https://www.wikidata.org/wiki/Q352090","display_name":"Smart Cache","level":5,"score":0.6045514345169067},{"id":"https://openalex.org/C201148951","wikidata":"https://www.wikidata.org/wiki/Q5015976","display_name":"Cache coloring","level":4,"score":0.5933575630187988},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.5810714364051819},{"id":"https://openalex.org/C88196245","wikidata":"https://www.wikidata.org/wiki/Q8034984","display_name":"Working set","level":2,"score":0.5141106247901917},{"id":"https://openalex.org/C36340418","wikidata":"https://www.wikidata.org/wiki/Q7124288","display_name":"Page cache","level":5,"score":0.513494074344635},{"id":"https://openalex.org/C133875982","wikidata":"https://www.wikidata.org/wiki/Q764810","display_name":"Shared memory","level":2,"score":0.4768185019493103},{"id":"https://openalex.org/C177264268","wikidata":"https://www.wikidata.org/wiki/Q1514741","display_name":"Set (abstract data type)","level":2,"score":0.4563307464122772},{"id":"https://openalex.org/C141917322","wikidata":"https://www.wikidata.org/wiki/Q1025017","display_name":"Cache coherence","level":5,"score":0.4205091893672943},{"id":"https://openalex.org/C189783530","wikidata":"https://www.wikidata.org/wiki/Q352090","display_name":"CPU cache","level":3,"score":0.3973340094089508},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.34083306789398193},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.3351007103919983},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.06199616193771362}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1145/1454115.1454145","is_oa":false,"landing_page_url":"https://doi.org/10.1145/1454115.1454145","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 17th international conference on Parallel architectures and compilation techniques","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":21,"referenced_works":["https://openalex.org/W1967474856","https://openalex.org/W1980419087","https://openalex.org/W1980670417","https://openalex.org/W2010843180","https://openalex.org/W2022740893","https://openalex.org/W2103397328","https://openalex.org/W2120692212","https://openalex.org/W2124350608","https://openalex.org/W2129548165","https://openalex.org/W2129816520","https://openalex.org/W2134633067","https://openalex.org/W2143773524","https://openalex.org/W2144941482","https://openalex.org/W2148954445","https://openalex.org/W2152061572","https://openalex.org/W2166620913","https://openalex.org/W2916411819","https://openalex.org/W3144376511","https://openalex.org/W4238816702","https://openalex.org/W4239813889","https://openalex.org/W6759615093"],"related_works":["https://openalex.org/W2088799683","https://openalex.org/W2290179447","https://openalex.org/W2130688751","https://openalex.org/W273173017","https://openalex.org/W4249918808","https://openalex.org/W127037959","https://openalex.org/W1521238853","https://openalex.org/W2793052975","https://openalex.org/W2083348328","https://openalex.org/W2160996172"],"abstract_inverted_index":{"Chip":[0],"Multiprocessors":[1],"(CMPs)":[2],"allow":[3],"different":[4],"applications":[5,14,64],"to":[6],"concurrently":[7],"execute":[8],"on":[9],"a":[10,22],"single":[11],"chip.":[12],"When":[13],"with":[15],"differing":[16],"demands":[17],"for":[18,21],"memory":[19],"compete":[20],"shared":[23,45,50],"cache,":[24],"the":[25,36,44,59,69,76,80],"conventional":[26],"LRU":[27],"replacement":[28],"policy":[29],"can":[30,53,66],"significantly":[31,55],"degrade":[32],"cache":[33,51,70],"performance":[34,52],"when":[35],"aggregate":[37],"working":[38,61,77],"set":[39,62,78],"size":[40],"is":[41],"greater":[42],"than":[43],"cache.":[46],"In":[47],"such":[48],"cases,":[49],"be":[54],"improved":[56],"by":[57],"preserving":[58,72],"entire":[60],"of":[63,75,79],"that":[65],"co-exist":[67],"in":[68],"and":[71],"some":[73],"portion":[74],"remaining":[81],"applications.":[82]},"counts_by_year":[{"year":2026,"cited_by_count":1},{"year":2024,"cited_by_count":1},{"year":2023,"cited_by_count":1},{"year":2022,"cited_by_count":1},{"year":2021,"cited_by_count":8},{"year":2020,"cited_by_count":6},{"year":2019,"cited_by_count":14},{"year":2018,"cited_by_count":18},{"year":2017,"cited_by_count":25},{"year":2016,"cited_by_count":33},{"year":2015,"cited_by_count":22},{"year":2014,"cited_by_count":25},{"year":2013,"cited_by_count":32},{"year":2012,"cited_by_count":36}],"updated_date":"2026-07-14T23:27:15.235271","created_date":"2025-10-10T00:00:00"}
