{"id":"https://openalex.org/W1973621760","doi":"https://doi.org/10.1145/1454115.1454144","title":"Leveraging on-chip networks for data cache migration in chip multiprocessors","display_name":"Leveraging on-chip networks for data cache migration in chip multiprocessors","publication_year":2008,"publication_date":"2008-10-25","ids":{"openalex":"https://openalex.org/W1973621760","doi":"https://doi.org/10.1145/1454115.1454144","mag":"1973621760"},"language":"en","primary_location":{"id":"doi:10.1145/1454115.1454144","is_oa":false,"landing_page_url":"https://doi.org/10.1145/1454115.1454144","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 17th international conference on Parallel architectures and compilation techniques","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5017210203","display_name":"Noel Eisley","orcid":null},"institutions":[{"id":"https://openalex.org/I20089843","display_name":"Princeton University","ror":"https://ror.org/00hx57361","country_code":"US","type":"education","lineage":["https://openalex.org/I20089843"]}],"countries":["US"],"is_corresponding":true,"raw_author_name":"Noel Eisley","raw_affiliation_strings":["Princeton University, Princeton, NJ, USA","Department of EE, Princeton University, NJ 08544, USA"],"affiliations":[{"raw_affiliation_string":"Princeton University, Princeton, NJ, USA","institution_ids":["https://openalex.org/I20089843"]},{"raw_affiliation_string":"Department of EE, Princeton University, NJ 08544, USA","institution_ids":["https://openalex.org/I20089843"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5057413185","display_name":"Li-Shiuan Peh","orcid":"https://orcid.org/0000-0001-9010-6519"},"institutions":[{"id":"https://openalex.org/I20089843","display_name":"Princeton University","ror":"https://ror.org/00hx57361","country_code":"US","type":"education","lineage":["https://openalex.org/I20089843"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Li-Shiuan Peh","raw_affiliation_strings":["Princeton University, Princeton, NJ, USA","Department of EE, Princeton University, NJ 08544, USA"],"affiliations":[{"raw_affiliation_string":"Princeton University, Princeton, NJ, USA","institution_ids":["https://openalex.org/I20089843"]},{"raw_affiliation_string":"Department of EE, Princeton University, NJ 08544, USA","institution_ids":["https://openalex.org/I20089843"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5004722925","display_name":"Li Shang","orcid":"https://orcid.org/0000-0003-3944-7531"},"institutions":[{"id":"https://openalex.org/I188538660","display_name":"University of Colorado Boulder","ror":"https://ror.org/02ttsq026","country_code":"US","type":"education","lineage":["https://openalex.org/I188538660"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Li Shang","raw_affiliation_strings":["University of Colorado - Boulder, Boulder, CO, USA","Dept. of ECE, University of Colorado, Boulder, 80309, USA"],"affiliations":[{"raw_affiliation_string":"University of Colorado - Boulder, Boulder, CO, USA","institution_ids":["https://openalex.org/I188538660"]},{"raw_affiliation_string":"Dept. of ECE, University of Colorado, Boulder, 80309, USA","institution_ids":["https://openalex.org/I188538660"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":3,"corresponding_author_ids":["https://openalex.org/A5017210203"],"corresponding_institution_ids":["https://openalex.org/I20089843"],"apc_list":null,"apc_paid":null,"fwci":6.2324,"has_fulltext":false,"cited_by_count":33,"citation_normalized_percentile":{"value":0.96485627,"is_in_top_1_percent":false,"is_in_top_10_percent":true},"cited_by_percentile_year":{"min":90,"max":99},"biblio":{"volume":null,"issue":null,"first_page":"197","last_page":"207"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9997000098228455,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10018","display_name":"Advancements in Battery Materials","score":0.9983000159263611,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7968600988388062},{"id":"https://openalex.org/keywords/cache","display_name":"Cache","score":0.6630822420120239},{"id":"https://openalex.org/keywords/bus-sniffing","display_name":"Bus sniffing","score":0.5525677800178528},{"id":"https://openalex.org/keywords/chip","display_name":"Chip","score":0.542608380317688},{"id":"https://openalex.org/keywords/cache-algorithms","display_name":"Cache algorithms","score":0.5329310297966003},{"id":"https://openalex.org/keywords/scalability","display_name":"Scalability","score":0.5328593254089355},{"id":"https://openalex.org/keywords/cache-pollution","display_name":"Cache pollution","score":0.5201157331466675},{"id":"https://openalex.org/keywords/cache-only-memory-architecture","display_name":"Cache-only memory architecture","score":0.5045396089553833},{"id":"https://openalex.org/keywords/cache-invalidation","display_name":"Cache invalidation","score":0.48322543501853943},{"id":"https://openalex.org/keywords/router","display_name":"Router","score":0.47581416368484497},{"id":"https://openalex.org/keywords/page-cache","display_name":"Page cache","score":0.4603317677974701},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.4574214518070221},{"id":"https://openalex.org/keywords/cache-coloring","display_name":"Cache coloring","score":0.4541359543800354},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.43070098757743835},{"id":"https://openalex.org/keywords/cpu-cache","display_name":"CPU cache","score":0.41534435749053955},{"id":"https://openalex.org/keywords/overhead","display_name":"Overhead (engineering)","score":0.4107773005962372},{"id":"https://openalex.org/keywords/cache-coherence","display_name":"Cache coherence","score":0.4107184410095215},{"id":"https://openalex.org/keywords/computer-network","display_name":"Computer network","score":0.21819055080413818},{"id":"https://openalex.org/keywords/operating-system","display_name":"Operating system","score":0.20096853375434875},{"id":"https://openalex.org/keywords/telecommunications","display_name":"Telecommunications","score":0.08664897084236145}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7968600988388062},{"id":"https://openalex.org/C115537543","wikidata":"https://www.wikidata.org/wiki/Q165596","display_name":"Cache","level":2,"score":0.6630822420120239},{"id":"https://openalex.org/C51185590","wikidata":"https://www.wikidata.org/wiki/Q1017228","display_name":"Bus sniffing","level":5,"score":0.5525677800178528},{"id":"https://openalex.org/C165005293","wikidata":"https://www.wikidata.org/wiki/Q1074500","display_name":"Chip","level":2,"score":0.542608380317688},{"id":"https://openalex.org/C38556500","wikidata":"https://www.wikidata.org/wiki/Q13404475","display_name":"Cache algorithms","level":4,"score":0.5329310297966003},{"id":"https://openalex.org/C48044578","wikidata":"https://www.wikidata.org/wiki/Q727490","display_name":"Scalability","level":2,"score":0.5328593254089355},{"id":"https://openalex.org/C113166858","wikidata":"https://www.wikidata.org/wiki/Q5015981","display_name":"Cache pollution","level":5,"score":0.5201157331466675},{"id":"https://openalex.org/C3720319","wikidata":"https://www.wikidata.org/wiki/Q5015937","display_name":"Cache-only memory architecture","level":5,"score":0.5045396089553833},{"id":"https://openalex.org/C25536678","wikidata":"https://www.wikidata.org/wiki/Q5015977","display_name":"Cache invalidation","level":5,"score":0.48322543501853943},{"id":"https://openalex.org/C2775896111","wikidata":"https://www.wikidata.org/wiki/Q642560","display_name":"Router","level":2,"score":0.47581416368484497},{"id":"https://openalex.org/C36340418","wikidata":"https://www.wikidata.org/wiki/Q7124288","display_name":"Page cache","level":5,"score":0.4603317677974701},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.4574214518070221},{"id":"https://openalex.org/C201148951","wikidata":"https://www.wikidata.org/wiki/Q5015976","display_name":"Cache coloring","level":4,"score":0.4541359543800354},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.43070098757743835},{"id":"https://openalex.org/C189783530","wikidata":"https://www.wikidata.org/wiki/Q352090","display_name":"CPU cache","level":3,"score":0.41534435749053955},{"id":"https://openalex.org/C2779960059","wikidata":"https://www.wikidata.org/wiki/Q7113681","display_name":"Overhead (engineering)","level":2,"score":0.4107773005962372},{"id":"https://openalex.org/C141917322","wikidata":"https://www.wikidata.org/wiki/Q1025017","display_name":"Cache coherence","level":5,"score":0.4107184410095215},{"id":"https://openalex.org/C31258907","wikidata":"https://www.wikidata.org/wiki/Q1301371","display_name":"Computer network","level":1,"score":0.21819055080413818},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.20096853375434875},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.08664897084236145}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1145/1454115.1454144","is_oa":false,"landing_page_url":"https://doi.org/10.1145/1454115.1454144","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 17th international conference on Parallel architectures and compilation techniques","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"id":"https://metadata.un.org/sdg/10","display_name":"Reduced inequalities","score":0.7699999809265137}],"awards":[],"funders":[{"id":"https://openalex.org/F4320314455","display_name":"Minist\u00e8re de l'\u00c9conomie, de la Science et de l'Innovation - Qu\u00e9bec","ror":null}],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":27,"referenced_works":["https://openalex.org/W38543604","https://openalex.org/W1555915743","https://openalex.org/W1562342676","https://openalex.org/W1838662863","https://openalex.org/W1983096721","https://openalex.org/W2029171059","https://openalex.org/W2030458955","https://openalex.org/W2037402372","https://openalex.org/W2054739713","https://openalex.org/W2079967491","https://openalex.org/W2096193215","https://openalex.org/W2100913437","https://openalex.org/W2102060420","https://openalex.org/W2117324528","https://openalex.org/W2136572251","https://openalex.org/W2139239342","https://openalex.org/W2143515003","https://openalex.org/W2158747750","https://openalex.org/W2170653240","https://openalex.org/W2171164959","https://openalex.org/W2243416539","https://openalex.org/W2911669905","https://openalex.org/W4239331546","https://openalex.org/W4248800093","https://openalex.org/W4255387252","https://openalex.org/W4292169167","https://openalex.org/W6633566297"],"related_works":["https://openalex.org/W2584505417","https://openalex.org/W2161101294","https://openalex.org/W2026179701","https://openalex.org/W4312759433","https://openalex.org/W2148571123","https://openalex.org/W4304166325","https://openalex.org/W4380881125","https://openalex.org/W2290179447","https://openalex.org/W2407815036","https://openalex.org/W2074625830"],"abstract_inverted_index":{"Recently,":[0],"chip":[1],"multiprocessors":[2],"(CMPs)":[3],"have":[4,103],"arisen":[5],"as":[6,57,73],"the":[7,96,122,158,165,168],"de":[8],"facto":[9],"design":[10],"for":[11],"modern":[12],"high-performance":[13],"processors,":[14],"with":[15,179],"increasing":[16],"core":[17,90,137],"counts.":[18],"An":[19],"important":[20],"property":[21],"of":[22,99,153,160,170,188],"CMPs":[23],"is":[24,39,55],"that":[25,146],"remote,":[26],"but":[27],"on-chip,":[28],"L2":[29,127],"cache":[30,71,128,132],"accesses":[31,163],"are":[32],"less":[33],"costly":[34,58],"than":[35,63,140],"off-chip":[36,161],"accesses;":[37],"this":[38,109],"in":[40,134,157],"contrast":[41],"to":[42,51,76,88,125],"earlier":[43],"chip-to-chip":[44],"or":[45],"board-to-board":[46],"multiprocessors,":[47],"where":[48],"an":[49,151],"access":[50],"a":[52,64,74,104,154,171,184],"remote":[53],"node":[54],"just":[56],"if":[59],"not":[60,86,94],"more":[61,78],"so":[62],"main":[65],"memory":[66,162],"access.":[67],"This":[68,175],"motivates":[69],"on-chip":[70,97,136],"migration":[72,106,115,173],"means":[75],"retain":[77],"data":[79],"on-chip.":[80],"However,":[81],"previously":[82],"proposed":[83],"techniques":[84],"do":[85,93],"scale":[87],"high":[89],"counts:":[91],"they":[92],"leverage":[95],"caches":[98],"all":[100],"cores":[101],"nor":[102],"scalable":[105],"mechanism.":[107],"In":[108],"paper":[110],"we":[111],"propose":[112],"ascalable":[113],"in-network":[114],"technique":[116,148],"which":[117],"uses":[118],"hints":[119],"embedded":[120],"within":[121],"router":[123],"microarchitecture":[124],"steer":[126],"evictions":[129],"towards":[130],"free/invalid":[131],"slots":[133],"any":[135],"cache,":[138],"rather":[139],"evicting":[141],"it":[142],"off-chip.":[143],"We":[144],"show":[145],"our":[147],"can":[149,176],"provide":[150],"average":[152],"19%":[155],"reduction":[156],"number":[159],"over":[164],"state-of-the-art,":[166],"beating":[167],"performance":[169],"pseudo-optimal":[172],"technique.":[174],"be":[177],"done":[178],"negligible":[180],"area":[181],"overhead":[182,187],"and":[183],"manageable":[185],"traffic":[186],"13.4%.":[189]},"counts_by_year":[{"year":2017,"cited_by_count":1},{"year":2015,"cited_by_count":1},{"year":2014,"cited_by_count":4},{"year":2013,"cited_by_count":4},{"year":2012,"cited_by_count":6}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}
