{"id":"https://openalex.org/W2120393760","doi":"https://doi.org/10.1145/1454115.1454138","title":"Improving support for locality and fine-grain sharing in chip multiprocessors","display_name":"Improving support for locality and fine-grain sharing in chip multiprocessors","publication_year":2008,"publication_date":"2008-10-25","ids":{"openalex":"https://openalex.org/W2120393760","doi":"https://doi.org/10.1145/1454115.1454138","mag":"2120393760"},"language":"en","primary_location":{"id":"doi:10.1145/1454115.1454138","is_oa":false,"landing_page_url":"https://doi.org/10.1145/1454115.1454138","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 17th international conference on Parallel architectures and compilation techniques","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5067019288","display_name":"Hemayet Hossain","orcid":"https://orcid.org/0000-0001-8759-9279"},"institutions":[{"id":"https://openalex.org/I5388228","display_name":"University of Rochester","ror":"https://ror.org/022kthw22","country_code":"US","type":"education","lineage":["https://openalex.org/I5388228"]}],"countries":["US"],"is_corresponding":true,"raw_author_name":"Hemayet Hossain","raw_affiliation_strings":["University of Rochester, Rochester, NY, USA"],"affiliations":[{"raw_affiliation_string":"University of Rochester, Rochester, NY, USA","institution_ids":["https://openalex.org/I5388228"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5013232946","display_name":"Sandhya Dwarkadas","orcid":"https://orcid.org/0000-0003-2631-8191"},"institutions":[{"id":"https://openalex.org/I5388228","display_name":"University of Rochester","ror":"https://ror.org/022kthw22","country_code":"US","type":"education","lineage":["https://openalex.org/I5388228"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Sandhya Dwarkadas","raw_affiliation_strings":["University of Rochester, Rochester, NY, USA"],"affiliations":[{"raw_affiliation_string":"University of Rochester, Rochester, NY, USA","institution_ids":["https://openalex.org/I5388228"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5078079786","display_name":"Michael Huang","orcid":"https://orcid.org/0000-0001-9799-2920"},"institutions":[{"id":"https://openalex.org/I5388228","display_name":"University of Rochester","ror":"https://ror.org/022kthw22","country_code":"US","type":"education","lineage":["https://openalex.org/I5388228"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Michael C. Huang","raw_affiliation_strings":["University of Rochester, Rochester, NY, USA"],"affiliations":[{"raw_affiliation_string":"University of Rochester, Rochester, NY, USA","institution_ids":["https://openalex.org/I5388228"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":3,"corresponding_author_ids":["https://openalex.org/A5067019288"],"corresponding_institution_ids":["https://openalex.org/I5388228"],"apc_list":null,"apc_paid":null,"fwci":3.8127,"has_fulltext":false,"cited_by_count":23,"citation_normalized_percentile":{"value":0.93736366,"is_in_top_1_percent":false,"is_in_top_10_percent":true},"cited_by_percentile_year":{"min":89,"max":98},"biblio":{"volume":null,"issue":null,"first_page":"155","last_page":"165"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10715","display_name":"Distributed and Parallel Computing Systems","score":0.9995999932289124,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11181","display_name":"Advanced Data Storage Technologies","score":0.9995999932289124,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.79585200548172},{"id":"https://openalex.org/keywords/exploit","display_name":"Exploit","score":0.6983316540718079},{"id":"https://openalex.org/keywords/mesi-protocol","display_name":"MESI protocol","score":0.6965728402137756},{"id":"https://openalex.org/keywords/cache-coherence","display_name":"Cache coherence","score":0.6730189323425293},{"id":"https://openalex.org/keywords/cache","display_name":"Cache","score":0.5783493518829346},{"id":"https://openalex.org/keywords/chip","display_name":"Chip","score":0.5043808221817017},{"id":"https://openalex.org/keywords/locality","display_name":"Locality","score":0.49630481004714966},{"id":"https://openalex.org/keywords/bus-sniffing","display_name":"Bus sniffing","score":0.48615118861198425},{"id":"https://openalex.org/keywords/latency","display_name":"Latency (audio)","score":0.4643673300743103},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.4563771188259125},{"id":"https://openalex.org/keywords/mesif-protocol","display_name":"MESIF protocol","score":0.4391844868659973},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.36808666586875916},{"id":"https://openalex.org/keywords/cpu-cache","display_name":"CPU cache","score":0.29805105924606323},{"id":"https://openalex.org/keywords/cache-algorithms","display_name":"Cache algorithms","score":0.23817205429077148},{"id":"https://openalex.org/keywords/telecommunications","display_name":"Telecommunications","score":0.08379125595092773}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.79585200548172},{"id":"https://openalex.org/C165696696","wikidata":"https://www.wikidata.org/wiki/Q11287","display_name":"Exploit","level":2,"score":0.6983316540718079},{"id":"https://openalex.org/C120936851","wikidata":"https://www.wikidata.org/wiki/Q1408065","display_name":"MESI protocol","level":5,"score":0.6965728402137756},{"id":"https://openalex.org/C141917322","wikidata":"https://www.wikidata.org/wiki/Q1025017","display_name":"Cache coherence","level":5,"score":0.6730189323425293},{"id":"https://openalex.org/C115537543","wikidata":"https://www.wikidata.org/wiki/Q165596","display_name":"Cache","level":2,"score":0.5783493518829346},{"id":"https://openalex.org/C165005293","wikidata":"https://www.wikidata.org/wiki/Q1074500","display_name":"Chip","level":2,"score":0.5043808221817017},{"id":"https://openalex.org/C2779808786","wikidata":"https://www.wikidata.org/wiki/Q6664603","display_name":"Locality","level":2,"score":0.49630481004714966},{"id":"https://openalex.org/C51185590","wikidata":"https://www.wikidata.org/wiki/Q1017228","display_name":"Bus sniffing","level":5,"score":0.48615118861198425},{"id":"https://openalex.org/C82876162","wikidata":"https://www.wikidata.org/wiki/Q17096504","display_name":"Latency (audio)","level":2,"score":0.4643673300743103},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.4563771188259125},{"id":"https://openalex.org/C199979278","wikidata":"https://www.wikidata.org/wiki/Q263221","display_name":"MESIF protocol","level":5,"score":0.4391844868659973},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.36808666586875916},{"id":"https://openalex.org/C189783530","wikidata":"https://www.wikidata.org/wiki/Q352090","display_name":"CPU cache","level":3,"score":0.29805105924606323},{"id":"https://openalex.org/C38556500","wikidata":"https://www.wikidata.org/wiki/Q13404475","display_name":"Cache algorithms","level":4,"score":0.23817205429077148},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.08379125595092773},{"id":"https://openalex.org/C138885662","wikidata":"https://www.wikidata.org/wiki/Q5891","display_name":"Philosophy","level":0,"score":0.0},{"id":"https://openalex.org/C38652104","wikidata":"https://www.wikidata.org/wiki/Q3510521","display_name":"Computer security","level":1,"score":0.0},{"id":"https://openalex.org/C41895202","wikidata":"https://www.wikidata.org/wiki/Q8162","display_name":"Linguistics","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1145/1454115.1454138","is_oa":false,"landing_page_url":"https://doi.org/10.1145/1454115.1454138","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 17th international conference on Parallel architectures and compilation techniques","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[{"id":"https://openalex.org/F4320330412","display_name":"Scheme for Promotion of Academic and Research Collaboration","ror":null}],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":35,"referenced_works":["https://openalex.org/W1855434625","https://openalex.org/W2012643955","https://openalex.org/W2022740893","https://openalex.org/W2025413686","https://openalex.org/W2037531986","https://openalex.org/W2039573521","https://openalex.org/W2052839611","https://openalex.org/W2055204455","https://openalex.org/W2073776178","https://openalex.org/W2078423579","https://openalex.org/W2096193215","https://openalex.org/W2108583124","https://openalex.org/W2110226069","https://openalex.org/W2112833506","https://openalex.org/W2117324528","https://openalex.org/W2118543332","https://openalex.org/W2120635877","https://openalex.org/W2122764141","https://openalex.org/W2126372249","https://openalex.org/W2127768834","https://openalex.org/W2133985894","https://openalex.org/W2134182085","https://openalex.org/W2135673469","https://openalex.org/W2142702271","https://openalex.org/W2143515003","https://openalex.org/W2160428323","https://openalex.org/W2162109942","https://openalex.org/W2164264749","https://openalex.org/W2171164959","https://openalex.org/W2218269467","https://openalex.org/W2243416539","https://openalex.org/W2911669905","https://openalex.org/W4248800093","https://openalex.org/W4253795537","https://openalex.org/W4255387252"],"related_works":["https://openalex.org/W2290195868","https://openalex.org/W2584505417","https://openalex.org/W4285204597","https://openalex.org/W1555453305","https://openalex.org/W3193874149","https://openalex.org/W2987765027","https://openalex.org/W2047210963","https://openalex.org/W2379215066","https://openalex.org/W1907826018","https://openalex.org/W2742883483"],"abstract_inverted_index":{"Both":[0],"commercial":[1],"and":[2,8,64],"scientific":[3],"workloads":[4],"benefit":[5],"from":[6],"concurrency":[7],"exhibit":[9],"data":[10],"sharing":[11,16,44],"across":[12],"threads/processes.":[13],"The":[14],"resulting":[15],"patterns":[17],"are":[18],"often":[19],"fine-grain,":[20],"with":[21],"the":[22,29,73,79,86],"modified":[23],"cache":[24,32],"lines":[25],"still":[26],"residing":[27],"in":[28,97],"writer's":[30],"primary":[31],"when":[33],"accessed.":[34],"Chip":[35],"multiprocessors":[36],"present":[37,60],"an":[38],"opportunity":[39],"to":[40,48,72,81,85,99],"optimize":[41],"for":[42],"fine-grain":[43,101],"using":[45],"direct":[46,83],"access":[47,84],"remote":[49,90],"processor":[50],"components":[51],"through":[52],"low-latency":[53],"on-chip":[54],"interconnects.":[55],"In":[56],"this":[57],"paper,":[58],"we":[59],"Adaptive":[61],"Replication,":[62],"Migration,":[63],"producer-Consumer":[65],"Optimization":[66],"(ARMCO),":[67],"a":[68],"coherence":[69,95],"protocol":[70],"that,":[71],"best":[74],"of":[75,89],"our":[76],"knowledge,":[77],"is":[78],"first":[80],"exploit":[82],"L1":[87],"caches":[88],"processors":[91],"(rather":[92],"than":[93],"via":[94],"mechanisms)":[96],"order":[98],"support":[100],"sharing.":[102]},"counts_by_year":[{"year":2022,"cited_by_count":1},{"year":2021,"cited_by_count":1},{"year":2015,"cited_by_count":2},{"year":2014,"cited_by_count":3},{"year":2013,"cited_by_count":1},{"year":2012,"cited_by_count":4}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}