{"id":"https://openalex.org/W2091580198","doi":"https://doi.org/10.1145/1450095.1450110","title":"Efficiency and scalability of barrier synchronization on NoC based many-core architectures","display_name":"Efficiency and scalability of barrier synchronization on NoC based many-core architectures","publication_year":2008,"publication_date":"2008-10-19","ids":{"openalex":"https://openalex.org/W2091580198","doi":"https://doi.org/10.1145/1450095.1450110","mag":"2091580198"},"language":"en","primary_location":{"id":"doi:10.1145/1450095.1450110","is_oa":false,"landing_page_url":"https://doi.org/10.1145/1450095.1450110","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 2008 international conference on Compilers, architectures and synthesis for embedded systems","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5111373927","display_name":"Oreste Villa","orcid":null},"institutions":[{"id":"https://openalex.org/I142606810","display_name":"Pacific Northwest National Laboratory","ror":"https://ror.org/05h992307","country_code":"US","type":"facility","lineage":["https://openalex.org/I1325736334","https://openalex.org/I1330989302","https://openalex.org/I142606810","https://openalex.org/I39565521"]}],"countries":["US"],"is_corresponding":true,"raw_author_name":"Oreste Villa","raw_affiliation_strings":["Pacific Northwest National Laboratory, Richland, WA, USA","Pacific Northwest National Laboratory, Richland, WA USA"],"affiliations":[{"raw_affiliation_string":"Pacific Northwest National Laboratory, Richland, WA, USA","institution_ids":["https://openalex.org/I142606810"]},{"raw_affiliation_string":"Pacific Northwest National Laboratory, Richland, WA USA","institution_ids":["https://openalex.org/I142606810"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5077005193","display_name":"Gianluca Palermo","orcid":"https://orcid.org/0000-0001-7955-8012"},"institutions":[{"id":"https://openalex.org/I93860229","display_name":"Politecnico di Milano","ror":"https://ror.org/01nffqt88","country_code":"IT","type":"education","lineage":["https://openalex.org/I93860229"]}],"countries":["IT"],"is_corresponding":false,"raw_author_name":"Gianluca Palermo","raw_affiliation_strings":["Politecnico di Milano, Milano, Italy"],"affiliations":[{"raw_affiliation_string":"Politecnico di Milano, Milano, Italy","institution_ids":["https://openalex.org/I93860229"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5031461662","display_name":"Cristina Silvano","orcid":"https://orcid.org/0000-0003-1668-0883"},"institutions":[{"id":"https://openalex.org/I93860229","display_name":"Politecnico di Milano","ror":"https://ror.org/01nffqt88","country_code":"IT","type":"education","lineage":["https://openalex.org/I93860229"]}],"countries":["IT"],"is_corresponding":false,"raw_author_name":"Cristina Silvano","raw_affiliation_strings":["Politecnico di Milano, Milano, Italy"],"affiliations":[{"raw_affiliation_string":"Politecnico di Milano, Milano, Italy","institution_ids":["https://openalex.org/I93860229"]}]}],"institutions":[],"countries_distinct_count":2,"institutions_distinct_count":3,"corresponding_author_ids":["https://openalex.org/A5111373927"],"corresponding_institution_ids":["https://openalex.org/I142606810"],"apc_list":null,"apc_paid":null,"fwci":4.3993,"has_fulltext":false,"cited_by_count":46,"citation_normalized_percentile":{"value":0.94708513,"is_in_top_1_percent":false,"is_in_top_10_percent":true},"cited_by_percentile_year":{"min":89,"max":99},"biblio":{"volume":null,"issue":null,"first_page":"81","last_page":"90"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9986000061035156,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10179","display_name":"Supercapacitor Materials and Fabrication","score":0.9958000183105469,"subfield":{"id":"https://openalex.org/subfields/2504","display_name":"Electronic, Optical and Magnetic Materials"},"field":{"id":"https://openalex.org/fields/25","display_name":"Materials Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7745264768600464},{"id":"https://openalex.org/keywords/scalability","display_name":"Scalability","score":0.7710026502609253},{"id":"https://openalex.org/keywords/network-topology","display_name":"Network topology","score":0.7574490308761597},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.5438722372055054},{"id":"https://openalex.org/keywords/network-on-a-chip","display_name":"Network on a chip","score":0.5131059885025024},{"id":"https://openalex.org/keywords/multi-core-processor","display_name":"Multi-core processor","score":0.5091027617454529},{"id":"https://openalex.org/keywords/benchmark","display_name":"Benchmark (surveying)","score":0.4977553188800812},{"id":"https://openalex.org/keywords/synchronization","display_name":"Synchronization (alternating current)","score":0.49191784858703613},{"id":"https://openalex.org/keywords/distributed-computing","display_name":"Distributed computing","score":0.4732537865638733},{"id":"https://openalex.org/keywords/topology","display_name":"Topology (electrical circuits)","score":0.45078858733177185},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.3506661057472229},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.32551783323287964},{"id":"https://openalex.org/keywords/computer-network","display_name":"Computer network","score":0.18218156695365906},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.10854852199554443}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7745264768600464},{"id":"https://openalex.org/C48044578","wikidata":"https://www.wikidata.org/wiki/Q727490","display_name":"Scalability","level":2,"score":0.7710026502609253},{"id":"https://openalex.org/C199845137","wikidata":"https://www.wikidata.org/wiki/Q145490","display_name":"Network topology","level":2,"score":0.7574490308761597},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.5438722372055054},{"id":"https://openalex.org/C128519102","wikidata":"https://www.wikidata.org/wiki/Q339554","display_name":"Network on a chip","level":2,"score":0.5131059885025024},{"id":"https://openalex.org/C78766204","wikidata":"https://www.wikidata.org/wiki/Q555032","display_name":"Multi-core processor","level":2,"score":0.5091027617454529},{"id":"https://openalex.org/C185798385","wikidata":"https://www.wikidata.org/wiki/Q1161707","display_name":"Benchmark (surveying)","level":2,"score":0.4977553188800812},{"id":"https://openalex.org/C2778562939","wikidata":"https://www.wikidata.org/wiki/Q1298791","display_name":"Synchronization (alternating current)","level":3,"score":0.49191784858703613},{"id":"https://openalex.org/C120314980","wikidata":"https://www.wikidata.org/wiki/Q180634","display_name":"Distributed computing","level":1,"score":0.4732537865638733},{"id":"https://openalex.org/C184720557","wikidata":"https://www.wikidata.org/wiki/Q7825049","display_name":"Topology (electrical circuits)","level":2,"score":0.45078858733177185},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.3506661057472229},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.32551783323287964},{"id":"https://openalex.org/C31258907","wikidata":"https://www.wikidata.org/wiki/Q1301371","display_name":"Computer network","level":1,"score":0.18218156695365906},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.10854852199554443},{"id":"https://openalex.org/C127162648","wikidata":"https://www.wikidata.org/wiki/Q16858953","display_name":"Channel (broadcasting)","level":2,"score":0.0},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.0},{"id":"https://openalex.org/C205649164","wikidata":"https://www.wikidata.org/wiki/Q1071","display_name":"Geography","level":0,"score":0.0},{"id":"https://openalex.org/C13280743","wikidata":"https://www.wikidata.org/wiki/Q131089","display_name":"Geodesy","level":1,"score":0.0},{"id":"https://openalex.org/C77088390","wikidata":"https://www.wikidata.org/wiki/Q8513","display_name":"Database","level":1,"score":0.0}],"mesh":[],"locations_count":2,"locations":[{"id":"doi:10.1145/1450095.1450110","is_oa":false,"landing_page_url":"https://doi.org/10.1145/1450095.1450110","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 2008 international conference on Compilers, architectures and synthesis for embedded systems","raw_type":"proceedings-article"},{"id":"pmh:oai:re.public.polimi.it:11311/501076","is_oa":false,"landing_page_url":"http://hdl.handle.net/11311/501076","pdf_url":null,"source":{"id":"https://openalex.org/S4306400312","display_name":"Virtual Community of Pathological Anatomy (University of Castilla La Mancha)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/I79189158","host_organization_name":"University of Castilla-La Mancha","host_organization_lineage":["https://openalex.org/I79189158"],"host_organization_lineage_names":[],"type":"repository"},"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"","raw_type":"info:eu-repo/semantics/conferenceObject"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":14,"referenced_works":["https://openalex.org/W1582835330","https://openalex.org/W1902879054","https://openalex.org/W1990305761","https://openalex.org/W2018307252","https://openalex.org/W2030907583","https://openalex.org/W2089155985","https://openalex.org/W2099399959","https://openalex.org/W2107702761","https://openalex.org/W2110200491","https://openalex.org/W2121082877","https://openalex.org/W2123184444","https://openalex.org/W2139356019","https://openalex.org/W2160642395","https://openalex.org/W2162847528"],"related_works":["https://openalex.org/W1980085932","https://openalex.org/W2594964164","https://openalex.org/W2030249421","https://openalex.org/W1966736993","https://openalex.org/W2022199660","https://openalex.org/W2547794540","https://openalex.org/W2161995522","https://openalex.org/W3023876411","https://openalex.org/W123152114","https://openalex.org/W4863605"],"abstract_inverted_index":{"Interconnects":[0],"based":[1,69,77],"on":[2,22,34,54,70,78],"Networks-on-Chip":[3],"are":[4],"an":[5],"appealing":[6],"solution":[7],"to":[8,44,105,158],"address":[9],"future":[10],"microprocessor":[11],"designs":[12],"where,":[13],"very":[14],"likely,":[15],"hundreds":[16],"of":[17,48,57,62,97,101,125,166],"cores":[18,102],"will":[19,37],"be":[20,38,179],"connected":[21,186],"a":[23,92,98,118,152],"single":[24],"chip.":[25],"A":[26],"fundamental":[27],"role":[28],"in":[29,66,147,172],"highly":[30,185],"parallelized":[31],"applications":[32],"running":[33],"many-core":[35,67],"architectures":[36,68],"played":[39],"by":[40],"barrier":[41,64,75,127,143],"primitives":[42],"used":[43],"synchronize":[45],"the":[46,55,58,123,164],"execution":[47],"parallel":[49],"processes.":[50],"This":[51],"paper":[52],"focuses":[53],"analysis":[56],"efficiency":[59,165],"and":[60,84,89,107,115,133,184],"scalability":[61,124],"different":[63,108,153],"implementations":[65,76],"NoCs.":[71],"Several":[72],"message":[73],"passing":[74],"four":[79],"algorithms":[80],"(all-to-all,":[81],"master-slave,":[82],"butterfly":[83],"tree)":[85],"have":[86],"been":[87],"implemented":[88,146],"evaluated":[90],"for":[91,128],"single-chip":[93],"target":[94],"architecture":[95],"composed":[96],"variable":[99],"number":[100],"(from":[103],"4":[104],"128)":[106],"network":[109,176],"topologies":[110,177],"(mesh,":[111],"torus,":[112],"ring,":[113],"clustered-ring":[114],"fat-tree).":[116],"Using":[117],"cycle-accurate":[119],"simulator,":[120],"we":[121],"show":[122,151],"each":[126,167],"every":[129],"NoC":[130],"topology,":[131],"analyzing":[132],"comparing":[134],"theoretical":[135],"with":[136,156],"real":[137],"behaviors.":[138],"We":[139,162],"observed":[140],"that":[141],"some":[142],"algorithms,":[144],"when":[145],"hardware":[148],"or":[149],"software,":[150],"scaling":[154],"behavior":[155],"respect":[157],"those":[159],"theoretically":[160],"expected.":[161],"evaluate":[163],"combination":[168],"topology-barrier,":[169],"demonstrating":[170],"that,":[171],"many":[173],"cases,":[174],"simple":[175],"can":[178],"more":[180],"efficient":[181],"than":[182],"complex":[183],"topologies.":[187]},"counts_by_year":[{"year":2023,"cited_by_count":1},{"year":2022,"cited_by_count":1},{"year":2021,"cited_by_count":1},{"year":2020,"cited_by_count":1},{"year":2018,"cited_by_count":5},{"year":2017,"cited_by_count":4},{"year":2016,"cited_by_count":3},{"year":2015,"cited_by_count":3},{"year":2014,"cited_by_count":4},{"year":2013,"cited_by_count":4},{"year":2012,"cited_by_count":7}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}