{"id":"https://openalex.org/W2009219733","doi":"https://doi.org/10.1145/1404371.1404415","title":"An improved and automated design tool for the optimization of CMOS OTAs using geometric programming","display_name":"An improved and automated design tool for the optimization of CMOS OTAs using geometric programming","publication_year":2008,"publication_date":"2008-09-01","ids":{"openalex":"https://openalex.org/W2009219733","doi":"https://doi.org/10.1145/1404371.1404415","mag":"2009219733"},"language":"en","primary_location":{"id":"doi:10.1145/1404371.1404415","is_oa":false,"landing_page_url":"https://doi.org/10.1145/1404371.1404415","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 21st annual symposium on Integrated circuits and system design","raw_type":"proceedings-article"},"type":"conference-paper","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5040069864","display_name":"Jorge Oliveros","orcid":"https://orcid.org/0000-0002-9293-9669"},"institutions":[{"id":"https://openalex.org/I115684694","display_name":"Industrial University of Santander","ror":"https://ror.org/00xc1d948","country_code":"CO","type":"education","lineage":["https://openalex.org/I115684694"]},{"id":"https://openalex.org/I17974374","display_name":"Universidade de S\u00e3o Paulo","ror":"https://ror.org/036rp1748","country_code":"BR","type":"education","lineage":["https://openalex.org/I17974374"]}],"countries":["BR","CO"],"is_corresponding":false,"raw_author_name":"Jorge Oliveros","raw_affiliation_strings":["University of S\u00e3o Paulo, S\u00e3o Paulo, Brazil and Industrial University of Santander, Bucaramanga, Colombia"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"University of S\u00e3o Paulo, S\u00e3o Paulo, Brazil and Industrial University of Santander, Bucaramanga, Colombia","institution_ids":["https://openalex.org/I115684694","https://openalex.org/I17974374"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5024715129","display_name":"Dwight Cabrera","orcid":null},"institutions":[{"id":"https://openalex.org/I115684694","display_name":"Industrial University of Santander","ror":"https://ror.org/00xc1d948","country_code":"CO","type":"education","lineage":["https://openalex.org/I115684694"]},{"id":"https://openalex.org/I17974374","display_name":"Universidade de S\u00e3o Paulo","ror":"https://ror.org/036rp1748","country_code":"BR","type":"education","lineage":["https://openalex.org/I17974374"]}],"countries":["BR","CO"],"is_corresponding":false,"raw_author_name":"Dwight Cabrera","raw_affiliation_strings":["University of S\u00e3o Paulo, S\u00e3o Paulo, Brazil and Industrial University of Santander, Bucaramanga, Colombia"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"University of S\u00e3o Paulo, S\u00e3o Paulo, Brazil and Industrial University of Santander, Bucaramanga, Colombia","institution_ids":["https://openalex.org/I115684694","https://openalex.org/I17974374"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5070510631","display_name":"Elkim Roa","orcid":"https://orcid.org/0000-0003-0290-7493"},"institutions":[{"id":"https://openalex.org/I115684694","display_name":"Industrial University of Santander","ror":"https://ror.org/00xc1d948","country_code":"CO","type":"education","lineage":["https://openalex.org/I115684694"]}],"countries":["CO"],"is_corresponding":false,"raw_author_name":"Elkim Roa","raw_affiliation_strings":["Industrial University of Santander, Bucaramanga, Colombia","Industrial University of Santander, Bucaramanga, Colombia#TAB#"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Industrial University of Santander, Bucaramanga, Colombia","institution_ids":["https://openalex.org/I115684694"]},{"raw_affiliation_string":"Industrial University of Santander, Bucaramanga, Colombia#TAB#","institution_ids":["https://openalex.org/I115684694"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5021177341","display_name":"Wilhelmus Van Noije","orcid":"https://orcid.org/0000-0002-9010-3083"},"institutions":[{"id":"https://openalex.org/I17974374","display_name":"Universidade de S\u00e3o Paulo","ror":"https://ror.org/036rp1748","country_code":"BR","type":"education","lineage":["https://openalex.org/I17974374"]}],"countries":["BR"],"is_corresponding":false,"raw_author_name":"Wilhelmus Van Noije","raw_affiliation_strings":["University of S\u00e3o Paulo, S\u00e3o Paulo, Brazil"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"University of S\u00e3o Paulo, S\u00e3o Paulo, Brazil","institution_ids":["https://openalex.org/I17974374"]}]}],"institutions":[],"countries_distinct_count":2,"institutions_distinct_count":2,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":null,"has_fulltext":false,"cited_by_count":13,"citation_normalized_percentile":null,"cited_by_percentile_year":null,"biblio":{"volume":null,"issue":null,"first_page":"146","last_page":"151"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9961000084877014,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/cmos","display_name":"CMOS","score":0.8145574927330017},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.5976188778877258},{"id":"https://openalex.org/keywords/geometric-programming","display_name":"Geometric programming","score":0.5607638359069824},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.5236034989356995},{"id":"https://openalex.org/keywords/bandwidth","display_name":"Bandwidth (computing)","score":0.4957481324672699},{"id":"https://openalex.org/keywords/integrated-circuit-design","display_name":"Integrated circuit design","score":0.461452841758728},{"id":"https://openalex.org/keywords/margin","display_name":"Margin (machine learning)","score":0.4431188702583313},{"id":"https://openalex.org/keywords/phase-margin","display_name":"Phase margin","score":0.4286285638809204},{"id":"https://openalex.org/keywords/power-consumption","display_name":"Power consumption","score":0.4233183264732361},{"id":"https://openalex.org/keywords/cad","display_name":"CAD","score":0.41510191559791565},{"id":"https://openalex.org/keywords/electronic-design-automation","display_name":"Electronic design automation","score":0.41193005442619324},{"id":"https://openalex.org/keywords/network-topology","display_name":"Network topology","score":0.4102822542190552},{"id":"https://openalex.org/keywords/power","display_name":"Power (physics)","score":0.4099541902542114},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.3763757348060608},{"id":"https://openalex.org/keywords/operational-amplifier","display_name":"Operational amplifier","score":0.16629084944725037},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.16324183344841003},{"id":"https://openalex.org/keywords/engineering-drawing","display_name":"Engineering drawing","score":0.1085067093372345}],"concepts":[{"id":"https://openalex.org/C46362747","wikidata":"https://www.wikidata.org/wiki/Q173431","display_name":"CMOS","level":2,"score":0.8145574927330017},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.5976188778877258},{"id":"https://openalex.org/C20729856","wikidata":"https://www.wikidata.org/wiki/Q2078279","display_name":"Geometric programming","level":2,"score":0.5607638359069824},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.5236034989356995},{"id":"https://openalex.org/C2776257435","wikidata":"https://www.wikidata.org/wiki/Q1576430","display_name":"Bandwidth (computing)","level":2,"score":0.4957481324672699},{"id":"https://openalex.org/C74524168","wikidata":"https://www.wikidata.org/wiki/Q1074539","display_name":"Integrated circuit design","level":2,"score":0.461452841758728},{"id":"https://openalex.org/C774472","wikidata":"https://www.wikidata.org/wiki/Q6760393","display_name":"Margin (machine learning)","level":2,"score":0.4431188702583313},{"id":"https://openalex.org/C81455027","wikidata":"https://www.wikidata.org/wiki/Q7180955","display_name":"Phase margin","level":5,"score":0.4286285638809204},{"id":"https://openalex.org/C2984118289","wikidata":"https://www.wikidata.org/wiki/Q29954","display_name":"Power consumption","level":3,"score":0.4233183264732361},{"id":"https://openalex.org/C194789388","wikidata":"https://www.wikidata.org/wiki/Q17855283","display_name":"CAD","level":2,"score":0.41510191559791565},{"id":"https://openalex.org/C64260653","wikidata":"https://www.wikidata.org/wiki/Q1194864","display_name":"Electronic design automation","level":2,"score":0.41193005442619324},{"id":"https://openalex.org/C199845137","wikidata":"https://www.wikidata.org/wiki/Q145490","display_name":"Network topology","level":2,"score":0.4102822542190552},{"id":"https://openalex.org/C163258240","wikidata":"https://www.wikidata.org/wiki/Q25342","display_name":"Power (physics)","level":2,"score":0.4099541902542114},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.3763757348060608},{"id":"https://openalex.org/C145366948","wikidata":"https://www.wikidata.org/wiki/Q178947","display_name":"Operational amplifier","level":4,"score":0.16629084944725037},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.16324183344841003},{"id":"https://openalex.org/C199639397","wikidata":"https://www.wikidata.org/wiki/Q1788588","display_name":"Engineering drawing","level":1,"score":0.1085067093372345},{"id":"https://openalex.org/C119857082","wikidata":"https://www.wikidata.org/wiki/Q2539","display_name":"Machine learning","level":1,"score":0.0},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.0},{"id":"https://openalex.org/C121332964","wikidata":"https://www.wikidata.org/wiki/Q413","display_name":"Physics","level":0,"score":0.0},{"id":"https://openalex.org/C62520636","wikidata":"https://www.wikidata.org/wiki/Q944","display_name":"Quantum mechanics","level":1,"score":0.0},{"id":"https://openalex.org/C31258907","wikidata":"https://www.wikidata.org/wiki/Q1301371","display_name":"Computer network","level":1,"score":0.0},{"id":"https://openalex.org/C194257627","wikidata":"https://www.wikidata.org/wiki/Q211554","display_name":"Amplifier","level":3,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1145/1404371.1404415","is_oa":false,"landing_page_url":"https://doi.org/10.1145/1404371.1404415","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 21st annual symposium on Integrated circuits and system design","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"id":"https://metadata.un.org/sdg/7","display_name":"Affordable and clean energy","score":0.8199999928474426}],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":12,"referenced_works":["https://openalex.org/W1562942484","https://openalex.org/W2038038283","https://openalex.org/W2105280352","https://openalex.org/W2106476087","https://openalex.org/W2147059000","https://openalex.org/W2171048418","https://openalex.org/W2296319761","https://openalex.org/W4243014205","https://openalex.org/W4250589301","https://openalex.org/W4285719527","https://openalex.org/W6675931987","https://openalex.org/W6685032277"],"related_works":["https://openalex.org/W3205162826","https://openalex.org/W2059530328","https://openalex.org/W2080428035","https://openalex.org/W2743305891","https://openalex.org/W3198354237","https://openalex.org/W3011978806","https://openalex.org/W4255738297","https://openalex.org/W2951650892","https://openalex.org/W2045647383","https://openalex.org/W3207169898"],"abstract_inverted_index":{"This":[0],"paper":[1],"presents":[2],"an":[3,138],"improved":[4],"methodology":[5,25],"to":[6,69,82],"automate":[7],"the":[8,12,94,103,117,121,124,132,153,157,169],"design":[9,83,99,154],"and":[10,40,101,123,141],"minimize":[11],"power":[13],"consumption":[14],"of":[15,166],"typical":[16,85],"CMOS":[17,144],"OTAs.":[18],"Using":[19],"a":[20,79],"geometric":[21,57],"program":[22],"formulation,":[23],"this":[24],"can":[26],"handle":[27],"simultaneously":[28],"several":[29],"performance":[30,118,126],"specifications":[31],"including":[32],"quiescent":[33],"power,":[34],"DC":[35],"gain,":[36],"unity-gain":[37],"bandwidth,":[38],"CMRR":[39],"phase":[41],"margin":[42],"among":[43],"others.":[44],"We":[45],"present":[46],"some":[47,67],"remarkable":[48],"considerations,":[49],"not":[50],"detailed":[51],"in":[52,131,143,168],"literature,":[53],"that":[54,152],"arise":[55],"when":[56],"programming":[58],"is":[59,127,160],"used":[60],"for":[61,97,137],"analog":[62],"circuit":[63],"design.":[64],"In":[65],"addition,":[66],"strategies":[68,78],"deal":[70],"with":[71,105,156,163],"related":[72],"problems":[73],"are":[74,147],"presented.":[75,148],"With":[76],"these":[77],"CAD":[80],"tool":[81,92,122,159],"three":[84],"OTAs":[86],"topologies":[87],"has":[88],"been":[89],"developed.":[90],"The":[91,113],"gives":[93],"optimal":[95],"values":[96],"all":[98],"variables":[100],"verifies":[102],"results":[104,136,150],"HSPICE":[106],"simulations":[107],"using":[108],"level":[109],"49":[110],"BSIM3v3":[111],"models.":[112],"reported":[114],"error":[115,165],"between":[116],"predicted":[119],"by":[120],"simulated":[125],"lower":[128],"than":[129],"10%":[130],"worst":[133],"case.":[134],"Measurement":[135],"OTA":[139],"designed":[140],"fabricated":[142],"0.35\u00bcm":[145],"technology":[146],"These":[149],"show":[151],"performed":[155],"automated":[158],"silicon":[161],"accurate,":[162],"relative":[164],"4%":[167],"optimized":[170],"specification.":[171]},"counts_by_year":[{"year":2019,"cited_by_count":1},{"year":2016,"cited_by_count":3},{"year":2015,"cited_by_count":1},{"year":2013,"cited_by_count":1}],"updated_date":"2026-07-14T23:27:15.235271","created_date":"2025-10-10T00:00:00"}
