{"id":"https://openalex.org/W2119350858","doi":"https://doi.org/10.1145/1393921.1394010","title":"Full-system chip multiprocessor power evaluations using FPGA-based emulation","display_name":"Full-system chip multiprocessor power evaluations using FPGA-based emulation","publication_year":2008,"publication_date":"2008-01-01","ids":{"openalex":"https://openalex.org/W2119350858","doi":"https://doi.org/10.1145/1393921.1394010","mag":"2119350858"},"language":"en","primary_location":{"id":"doi:10.1145/1393921.1394010","is_oa":false,"landing_page_url":"https://doi.org/10.1145/1393921.1394010","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceeding of the thirteenth international symposium on Low power electronics and design - ISLPED '08","raw_type":"proceedings-article"},"type":"conference-paper","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5019487275","display_name":"Abhishek Bhattacharjee","orcid":"https://orcid.org/0000-0003-2742-2679"},"institutions":[{"id":"https://openalex.org/I20089843","display_name":"Princeton University","ror":"https://ror.org/00hx57361","country_code":"US","type":"education","lineage":["https://openalex.org/I20089843"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Abhishek Bhattacharjee","raw_affiliation_strings":["Dept. of Electr. Eng., Princeton Univ., Princeton, NJ, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Dept. of Electr. Eng., Princeton Univ., Princeton, NJ, USA","institution_ids":["https://openalex.org/I20089843"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5021010568","display_name":"Gilberto Contreras","orcid":null},"institutions":[{"id":"https://openalex.org/I20089843","display_name":"Princeton University","ror":"https://ror.org/00hx57361","country_code":"US","type":"education","lineage":["https://openalex.org/I20089843"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Gilberto Contreras","raw_affiliation_strings":["Dept. of Electr. Eng., Princeton Univ., Princeton, NJ, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Dept. of Electr. Eng., Princeton Univ., Princeton, NJ, USA","institution_ids":["https://openalex.org/I20089843"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5002015508","display_name":"Margaret Martonosi","orcid":"https://orcid.org/0000-0001-9683-8032"},"institutions":[{"id":"https://openalex.org/I20089843","display_name":"Princeton University","ror":"https://ror.org/00hx57361","country_code":"US","type":"education","lineage":["https://openalex.org/I20089843"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Margaret Martonosi","raw_affiliation_strings":["Dept. of Electr. Eng., Princeton Univ., Princeton, NJ, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Dept. of Electr. Eng., Princeton Univ., Princeton, NJ, USA","institution_ids":["https://openalex.org/I20089843"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":1,"corresponding_author_ids":[],"corresponding_institution_ids":["https://openalex.org/I20089843"],"apc_list":null,"apc_paid":null,"fwci":2.2547,"has_fulltext":false,"cited_by_count":41,"citation_normalized_percentile":{"value":0.89345064,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":99},"biblio":{"volume":null,"issue":null,"first_page":"335","last_page":"335"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9994999766349792,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.9991000294685364,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/emulation","display_name":"Emulation","score":0.8382706642150879},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.7389259934425354},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7283737659454346},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.6730936765670776},{"id":"https://openalex.org/keywords/multiprocessing","display_name":"Multiprocessing","score":0.6522050499916077},{"id":"https://openalex.org/keywords/system-on-a-chip","display_name":"System on a chip","score":0.567227840423584},{"id":"https://openalex.org/keywords/chip","display_name":"Chip","score":0.47621068358421326},{"id":"https://openalex.org/keywords/hardware-emulation","display_name":"Hardware emulation","score":0.41117554903030396},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.4051894545555115},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.3064500391483307},{"id":"https://openalex.org/keywords/telecommunications","display_name":"Telecommunications","score":0.06812641024589539}],"concepts":[{"id":"https://openalex.org/C149810388","wikidata":"https://www.wikidata.org/wiki/Q5374873","display_name":"Emulation","level":2,"score":0.8382706642150879},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.7389259934425354},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7283737659454346},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.6730936765670776},{"id":"https://openalex.org/C4822641","wikidata":"https://www.wikidata.org/wiki/Q846651","display_name":"Multiprocessing","level":2,"score":0.6522050499916077},{"id":"https://openalex.org/C118021083","wikidata":"https://www.wikidata.org/wiki/Q610398","display_name":"System on a chip","level":2,"score":0.567227840423584},{"id":"https://openalex.org/C165005293","wikidata":"https://www.wikidata.org/wiki/Q1074500","display_name":"Chip","level":2,"score":0.47621068358421326},{"id":"https://openalex.org/C94115699","wikidata":"https://www.wikidata.org/wiki/Q5656406","display_name":"Hardware emulation","level":3,"score":0.41117554903030396},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.4051894545555115},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.3064500391483307},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.06812641024589539},{"id":"https://openalex.org/C50522688","wikidata":"https://www.wikidata.org/wiki/Q189833","display_name":"Economic growth","level":1,"score":0.0},{"id":"https://openalex.org/C162324750","wikidata":"https://www.wikidata.org/wiki/Q8134","display_name":"Economics","level":0,"score":0.0}],"mesh":[],"locations_count":2,"locations":[{"id":"doi:10.1145/1393921.1394010","is_oa":false,"landing_page_url":"https://doi.org/10.1145/1393921.1394010","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceeding of the thirteenth international symposium on Low power electronics and design - ISLPED '08","raw_type":"proceedings-article"},{"id":"pmh:oai:CiteSeerX.psu:10.1.1.225.8051","is_oa":false,"landing_page_url":"http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.225.8051","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"http://www.cs.rutgers.edu/%7Eabhib/abhib-islped08.pdf","raw_type":"text"}],"best_oa_location":null,"sustainable_development_goals":[{"id":"https://metadata.un.org/sdg/9","display_name":"Industry, innovation and infrastructure","score":0.5099999904632568}],"awards":[],"funders":[{"id":"https://openalex.org/F4320306076","display_name":"National Science Foundation","ror":"https://ror.org/021nxhr62"}],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":23,"referenced_works":["https://openalex.org/W1978507093","https://openalex.org/W2002072104","https://openalex.org/W2014371209","https://openalex.org/W2033708281","https://openalex.org/W2066339098","https://openalex.org/W2095942479","https://openalex.org/W2102727118","https://openalex.org/W2121304948","https://openalex.org/W2123853086","https://openalex.org/W2124220432","https://openalex.org/W2132471117","https://openalex.org/W2133602216","https://openalex.org/W2135948795","https://openalex.org/W2137280659","https://openalex.org/W2148795361","https://openalex.org/W2149813938","https://openalex.org/W2150862507","https://openalex.org/W2154857344","https://openalex.org/W2164264749","https://openalex.org/W2169875292","https://openalex.org/W2462402886","https://openalex.org/W3148862943","https://openalex.org/W4285719527"],"related_works":["https://openalex.org/W2133965417","https://openalex.org/W119599369","https://openalex.org/W2113648965","https://openalex.org/W2102046644","https://openalex.org/W2062495483","https://openalex.org/W2140894580","https://openalex.org/W2169782229","https://openalex.org/W4245445873","https://openalex.org/W2156360978","https://openalex.org/W1973113362"],"abstract_inverted_index":{"The":[0],"design":[1,38],"process":[2,117],"for":[3,113],"chip":[4],"multiprocessors":[5],"(CMPs)":[6],"requires":[7],"extremely":[8],"long":[9],"simulation":[10],"times":[11],"to":[12,63,75,80,115],"explore":[13],"performance,":[14],"power,":[15],"and":[16,41,97,131,136],"thermal":[17,132],"issues,":[18],"particularly":[19],"when":[20],"operating":[21,138],"system":[22,107],"(OS)":[23],"effects":[24],"are":[25],"included.":[26],"In":[27,100],"response,":[28],"our":[29,86,105],"novel":[30],"FPGA-based":[31],"emulation":[32],"methodology":[33,126],"models":[34,56],"a":[35,90],"full":[36],"CMP":[37,121],"including":[39],"applications":[40],"an":[42,101],"OS.":[43],"Activity":[44],"counters":[45],"programmed":[46],"into":[47],"the":[48,120],"cores":[49],"feed":[50],"per-component":[51],"microarchitectural":[52],"power":[53,130],"models.":[54],"These":[55],"achieve":[57],"under":[58],"10":[59],"%":[60],"error":[61],"compared":[62,79],"detailed":[64,129],"gate-level":[65],"simulations.":[66,83],"Our":[67],"method":[68],"retains":[69],"software":[70,82],"flexibility,":[71],"but":[72],"offers":[73],"up":[74],"35":[76],"\u00d7":[77],"speedup":[78],"full-system":[81],"We":[84],"present":[85],"approach":[87],"by":[88],"emulating":[89],"2-core":[91],"Leon3":[92],"cache-coherent":[93],"multiprocessor":[94],"running":[95],"Linux":[96],"parallel":[98],"benchmarks.":[99],"example":[102],"case":[103],"study,":[104],"emulated":[106],"uses":[108],"activity":[109],"counts":[110],"(a":[111],"proxy":[112],"temperature)":[114],"guide":[116],"migration":[118],"between":[119],"cores.":[122],"Overall,":[123],"this":[124],"paper\u2019s":[125],"makes":[127],"possible":[128],"studies":[133],"of":[134],"CMPs":[135],"their":[137],"systems.":[139]},"counts_by_year":[{"year":2023,"cited_by_count":1},{"year":2022,"cited_by_count":1},{"year":2019,"cited_by_count":2},{"year":2018,"cited_by_count":1},{"year":2017,"cited_by_count":2},{"year":2016,"cited_by_count":6},{"year":2015,"cited_by_count":5},{"year":2014,"cited_by_count":4},{"year":2013,"cited_by_count":3},{"year":2012,"cited_by_count":4}],"updated_date":"2026-07-29T14:22:42.915294","created_date":"2025-10-10T00:00:00"}
