{"id":"https://openalex.org/W1983435243","doi":"https://doi.org/10.1145/1393921.1393957","title":"Low power design under parameter variations","display_name":"Low power design under parameter variations","publication_year":2008,"publication_date":"2008-01-01","ids":{"openalex":"https://openalex.org/W1983435243","doi":"https://doi.org/10.1145/1393921.1393957","mag":"1983435243"},"language":"en","primary_location":{"id":"doi:10.1145/1393921.1393957","is_oa":false,"landing_page_url":"https://doi.org/10.1145/1393921.1393957","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceeding of the thirteenth international symposium on Low power electronics and design - ISLPED '08","raw_type":"proceedings-article"},"type":"conference-abstract","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5039442844","display_name":"Swarup Bhunia","orcid":"https://orcid.org/0000-0001-6082-6961"},"institutions":[{"id":"https://openalex.org/I58956616","display_name":"Case Western Reserve University","ror":"https://ror.org/051fd9666","country_code":"US","type":"education","lineage":["https://openalex.org/I58956616"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Swarup Bhunia","raw_affiliation_strings":["Case Western Reserve University, Cleveland, OH, USA","Electr. Eng. & Comput. Sci., Case Western Reserve Univ., Cleveland, OH, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Case Western Reserve University, Cleveland, OH, USA","institution_ids":["https://openalex.org/I58956616"]},{"raw_affiliation_string":"Electr. Eng. & Comput. Sci., Case Western Reserve Univ., Cleveland, OH, USA","institution_ids":["https://openalex.org/I58956616"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5031161187","display_name":"Kaushik Roy","orcid":"https://orcid.org/0000-0002-0735-9695"},"institutions":[{"id":"https://openalex.org/I219193219","display_name":"Purdue University West Lafayette","ror":"https://ror.org/02dqehb95","country_code":"US","type":"education","lineage":["https://openalex.org/I219193219"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Kaushik Roy","raw_affiliation_strings":["Purdue University, West Lafayette, IN, USA","Electr. & Comput. Eng., Purdue Univ., West Lafayette, IN, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Purdue University, West Lafayette, IN, USA","institution_ids":["https://openalex.org/I219193219"]},{"raw_affiliation_string":"Electr. & Comput. Eng., Purdue Univ., West Lafayette, IN, USA","institution_ids":["https://openalex.org/I219193219"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":2,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":null,"has_fulltext":false,"cited_by_count":0,"citation_normalized_percentile":null,"cited_by_percentile_year":null,"biblio":{"volume":null,"issue":null,"first_page":"137","last_page":"137"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10558","display_name":"Advancements in Semiconductor Devices and Circuit Design","score":0.9991999864578247,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9986000061035156,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/process-variation","display_name":"Process variation","score":0.6631861925125122},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.6209388375282288},{"id":"https://openalex.org/keywords/robustness","display_name":"Robustness (evolution)","score":0.5585687160491943},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.5535540580749512},{"id":"https://openalex.org/keywords/parametric-statistics","display_name":"Parametric statistics","score":0.5390583276748657},{"id":"https://openalex.org/keywords/design-flow","display_name":"Design flow","score":0.49701741337776184},{"id":"https://openalex.org/keywords/logic-synthesis","display_name":"Logic synthesis","score":0.48834583163261414},{"id":"https://openalex.org/keywords/circuit-design","display_name":"Circuit design","score":0.4875637888908386},{"id":"https://openalex.org/keywords/integrated-circuit-design","display_name":"Integrated circuit design","score":0.4571002721786499},{"id":"https://openalex.org/keywords/dynamic-demand","display_name":"Dynamic demand","score":0.42044228315353394},{"id":"https://openalex.org/keywords/process-corners","display_name":"Process corners","score":0.4124000668525696},{"id":"https://openalex.org/keywords/logic-gate","display_name":"Logic gate","score":0.3790256977081299},{"id":"https://openalex.org/keywords/power","display_name":"Power (physics)","score":0.3653879165649414},{"id":"https://openalex.org/keywords/integrated-circuit","display_name":"Integrated circuit","score":0.30768316984176636},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.2130025327205658},{"id":"https://openalex.org/keywords/process","display_name":"Process (computing)","score":0.18524935841560364},{"id":"https://openalex.org/keywords/mathematics","display_name":"Mathematics","score":0.117926687002182}],"concepts":[{"id":"https://openalex.org/C93389723","wikidata":"https://www.wikidata.org/wiki/Q7247313","display_name":"Process variation","level":3,"score":0.6631861925125122},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6209388375282288},{"id":"https://openalex.org/C63479239","wikidata":"https://www.wikidata.org/wiki/Q7353546","display_name":"Robustness (evolution)","level":3,"score":0.5585687160491943},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.5535540580749512},{"id":"https://openalex.org/C117251300","wikidata":"https://www.wikidata.org/wiki/Q1849855","display_name":"Parametric statistics","level":2,"score":0.5390583276748657},{"id":"https://openalex.org/C37135326","wikidata":"https://www.wikidata.org/wiki/Q931942","display_name":"Design flow","level":2,"score":0.49701741337776184},{"id":"https://openalex.org/C157922185","wikidata":"https://www.wikidata.org/wiki/Q173198","display_name":"Logic synthesis","level":3,"score":0.48834583163261414},{"id":"https://openalex.org/C190560348","wikidata":"https://www.wikidata.org/wiki/Q3245116","display_name":"Circuit design","level":2,"score":0.4875637888908386},{"id":"https://openalex.org/C74524168","wikidata":"https://www.wikidata.org/wiki/Q1074539","display_name":"Integrated circuit design","level":2,"score":0.4571002721786499},{"id":"https://openalex.org/C45872418","wikidata":"https://www.wikidata.org/wiki/Q5318966","display_name":"Dynamic demand","level":3,"score":0.42044228315353394},{"id":"https://openalex.org/C192615534","wikidata":"https://www.wikidata.org/wiki/Q7247268","display_name":"Process corners","level":3,"score":0.4124000668525696},{"id":"https://openalex.org/C131017901","wikidata":"https://www.wikidata.org/wiki/Q170451","display_name":"Logic gate","level":2,"score":0.3790256977081299},{"id":"https://openalex.org/C163258240","wikidata":"https://www.wikidata.org/wiki/Q25342","display_name":"Power (physics)","level":2,"score":0.3653879165649414},{"id":"https://openalex.org/C530198007","wikidata":"https://www.wikidata.org/wiki/Q80831","display_name":"Integrated circuit","level":2,"score":0.30768316984176636},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.2130025327205658},{"id":"https://openalex.org/C98045186","wikidata":"https://www.wikidata.org/wiki/Q205663","display_name":"Process (computing)","level":2,"score":0.18524935841560364},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.117926687002182},{"id":"https://openalex.org/C185592680","wikidata":"https://www.wikidata.org/wiki/Q2329","display_name":"Chemistry","level":0,"score":0.0},{"id":"https://openalex.org/C55493867","wikidata":"https://www.wikidata.org/wiki/Q7094","display_name":"Biochemistry","level":1,"score":0.0},{"id":"https://openalex.org/C104317684","wikidata":"https://www.wikidata.org/wiki/Q7187","display_name":"Gene","level":2,"score":0.0},{"id":"https://openalex.org/C105795698","wikidata":"https://www.wikidata.org/wiki/Q12483","display_name":"Statistics","level":1,"score":0.0},{"id":"https://openalex.org/C62520636","wikidata":"https://www.wikidata.org/wiki/Q944","display_name":"Quantum mechanics","level":1,"score":0.0},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.0},{"id":"https://openalex.org/C121332964","wikidata":"https://www.wikidata.org/wiki/Q413","display_name":"Physics","level":0,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1145/1393921.1393957","is_oa":false,"landing_page_url":"https://doi.org/10.1145/1393921.1393957","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceeding of the thirteenth international symposium on Low power electronics and design - ISLPED '08","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":0,"referenced_works":[],"related_works":["https://openalex.org/W1526857568","https://openalex.org/W2525077515","https://openalex.org/W2118152793","https://openalex.org/W2141625582","https://openalex.org/W4253195573","https://openalex.org/W2020934033","https://openalex.org/W4388000032","https://openalex.org/W2037625031","https://openalex.org/W2161524358","https://openalex.org/W2129294024"],"abstract_inverted_index":{"Design":[0,77],"considerations":[1],"for":[2,47],"low-power":[3,154],"operations":[4],"and":[5,24,57,60,74,114,131,144,155],"robustness":[6],"with":[7,108,126],"respect":[8],"to":[9,69,79,106,142],"variations":[10,111],"typically":[11],"impose":[12],"contradictory":[13],"design":[14,17,45,59,67],"requirements.":[15],"Low-power":[16],"techniques":[18,46,78,92],"such":[19,152],"as":[20,64,66,86,88,153],"voltage":[21,94],"scaling,":[22,95],"dual-Vth":[23],"gate":[25],"sizing":[26],"can":[27],"have":[28],"large":[29],"negative":[30],"impact":[31],"on":[32,43,128],"parametric":[33,83],"yield":[34,84],"under":[35,50,82],"process":[36,90],"variations.":[37,52],"In":[38],"this":[39],"tutorial,":[40],"we":[41,135],"focus":[42],"circuit/architectural":[44],"low":[48,72],"power":[49,73,81],"parameter":[51,110],"We":[53],"consider":[54],"both":[55],"logic":[56,100,113],"memory":[58,115],"encompass":[61],"modeling,":[62],"analysis":[63],"well":[65,87],"methodology":[68],"simultaneously":[70],"achieve":[71],"variation":[75,156],"tolerance.":[76],"minimize":[80],"constraint":[85],"major":[89],"adaptation":[91,141],"using":[93],"adaptive":[96],"body":[97,132],"biasing":[98],"or":[99],"restructuring":[101],"will":[102,123,136],"be":[103,124],"presented.":[104],"Techniques":[105],"deal":[107],"within-die":[109],"in":[112,149],"circuits":[116],"primarily":[117],"caused":[118],"by":[119],"random":[120],"dopant":[121],"fluctuations":[122],"discussed":[125],"emphasis":[127],"frequency":[129],"assignments":[130],"biasing.":[133],"Finally,":[134],"discuss":[137],"temperature-aware":[138],"design,":[139],"dynamic":[140],"temperature":[143],"cover":[145],"on-going":[146],"research":[147],"activities":[148],"related":[150],"area":[151],"tolerant":[157],"multi-core":[158],"processor":[159],"design.":[160]},"counts_by_year":[],"updated_date":"2026-07-14T23:27:15.235271","created_date":"2025-10-10T00:00:00"}