{"id":"https://openalex.org/W2019881864","doi":"https://doi.org/10.1145/1391469.1391652","title":"Circuit-wise buffer insertion and gate sizing algorithm with scalability","display_name":"Circuit-wise buffer insertion and gate sizing algorithm with scalability","publication_year":2008,"publication_date":"2008-06-08","ids":{"openalex":"https://openalex.org/W2019881864","doi":"https://doi.org/10.1145/1391469.1391652","mag":"2019881864"},"language":"en","primary_location":{"id":"doi:10.1145/1391469.1391652","is_oa":false,"landing_page_url":"https://doi.org/10.1145/1391469.1391652","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 45th annual Design Automation Conference","raw_type":"proceedings-article"},"type":"conference-paper","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5114017767","display_name":"Zhanyuan Jiang","orcid":null},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"Zhanyuan Jiang","raw_affiliation_strings":["Texas A&amp;M University, College Station, Texas and Atoptech, Inc., Santa Clara, California"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Texas A&amp;M University, College Station, Texas and Atoptech, Inc., Santa Clara, California","institution_ids":[]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5078773079","display_name":"Weiping Shi","orcid":"https://orcid.org/0000-0001-9773-9255"},"institutions":[{"id":"https://openalex.org/I91045830","display_name":"Texas A&M University","ror":"https://ror.org/01f5ytq51","country_code":"US","type":"education","lineage":["https://openalex.org/I91045830"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Weiping Shi","raw_affiliation_strings":["Texas A&amp;M University, College Station, Texas"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Texas A&amp;M University, College Station, Texas","institution_ids":["https://openalex.org/I91045830"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":1,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":0.9489,"has_fulltext":false,"cited_by_count":5,"citation_normalized_percentile":{"value":0.67880687,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":94},"biblio":{"volume":null,"issue":null,"first_page":"708","last_page":"713"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9994999766349792,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10558","display_name":"Advancements in Semiconductor Devices and Circuit Design","score":0.9984999895095825,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7947978973388672},{"id":"https://openalex.org/keywords/scalability","display_name":"Scalability","score":0.784044623374939},{"id":"https://openalex.org/keywords/buffer","display_name":"Buffer (optical fiber)","score":0.73482346534729},{"id":"https://openalex.org/keywords/heuristics","display_name":"Heuristics","score":0.7096893787384033},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.5280709266662598},{"id":"https://openalex.org/keywords/sizing","display_name":"Sizing","score":0.5082587599754333},{"id":"https://openalex.org/keywords/electronic-circuit","display_name":"Electronic circuit","score":0.4934953451156616},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.47347772121429443},{"id":"https://openalex.org/keywords/logic-gate","display_name":"Logic gate","score":0.4501391351222992},{"id":"https://openalex.org/keywords/heuristic","display_name":"Heuristic","score":0.4353320002555847},{"id":"https://openalex.org/keywords/algorithm-design","display_name":"Algorithm design","score":0.42804357409477234},{"id":"https://openalex.org/keywords/distributed-computing","display_name":"Distributed computing","score":0.35445597767829895},{"id":"https://openalex.org/keywords/computer-engineering","display_name":"Computer engineering","score":0.33982357382774353},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.1071513295173645},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.08079206943511963}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7947978973388672},{"id":"https://openalex.org/C48044578","wikidata":"https://www.wikidata.org/wiki/Q727490","display_name":"Scalability","level":2,"score":0.784044623374939},{"id":"https://openalex.org/C145018004","wikidata":"https://www.wikidata.org/wiki/Q4985944","display_name":"Buffer (optical fiber)","level":2,"score":0.73482346534729},{"id":"https://openalex.org/C127705205","wikidata":"https://www.wikidata.org/wiki/Q5748245","display_name":"Heuristics","level":2,"score":0.7096893787384033},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.5280709266662598},{"id":"https://openalex.org/C2777767291","wikidata":"https://www.wikidata.org/wiki/Q1080291","display_name":"Sizing","level":2,"score":0.5082587599754333},{"id":"https://openalex.org/C134146338","wikidata":"https://www.wikidata.org/wiki/Q1815901","display_name":"Electronic circuit","level":2,"score":0.4934953451156616},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.47347772121429443},{"id":"https://openalex.org/C131017901","wikidata":"https://www.wikidata.org/wiki/Q170451","display_name":"Logic gate","level":2,"score":0.4501391351222992},{"id":"https://openalex.org/C173801870","wikidata":"https://www.wikidata.org/wiki/Q201413","display_name":"Heuristic","level":2,"score":0.4353320002555847},{"id":"https://openalex.org/C106516650","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm design","level":2,"score":0.42804357409477234},{"id":"https://openalex.org/C120314980","wikidata":"https://www.wikidata.org/wiki/Q180634","display_name":"Distributed computing","level":1,"score":0.35445597767829895},{"id":"https://openalex.org/C113775141","wikidata":"https://www.wikidata.org/wiki/Q428691","display_name":"Computer engineering","level":1,"score":0.33982357382774353},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.1071513295173645},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.08079206943511963},{"id":"https://openalex.org/C154945302","wikidata":"https://www.wikidata.org/wiki/Q11660","display_name":"Artificial intelligence","level":1,"score":0.0},{"id":"https://openalex.org/C142362112","wikidata":"https://www.wikidata.org/wiki/Q735","display_name":"Art","level":0,"score":0.0},{"id":"https://openalex.org/C153349607","wikidata":"https://www.wikidata.org/wiki/Q36649","display_name":"Visual arts","level":1,"score":0.0},{"id":"https://openalex.org/C77088390","wikidata":"https://www.wikidata.org/wiki/Q8513","display_name":"Database","level":1,"score":0.0},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.0},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1145/1391469.1391652","is_oa":false,"landing_page_url":"https://doi.org/10.1145/1391469.1391652","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 45th annual Design Automation Conference","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[{"id":"https://openalex.org/G1960993011","display_name":null,"funder_award_id":"2004-TJ-1205","funder_id":"https://openalex.org/F4320306087","funder_display_name":"Semiconductor Research Corporation"}],"funders":[{"id":"https://openalex.org/F4320306087","display_name":"Semiconductor Research Corporation","ror":"https://ror.org/047z4n946"}],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":15,"referenced_works":["https://openalex.org/W1569550779","https://openalex.org/W2012173826","https://openalex.org/W2071649027","https://openalex.org/W2083404205","https://openalex.org/W2118412523","https://openalex.org/W2123316553","https://openalex.org/W2133171792","https://openalex.org/W2135250302","https://openalex.org/W2136176071","https://openalex.org/W2141907973","https://openalex.org/W2160252016","https://openalex.org/W2164824977","https://openalex.org/W2178990935","https://openalex.org/W2180582810","https://openalex.org/W4231702789"],"related_works":["https://openalex.org/W2375311683","https://openalex.org/W2366062860","https://openalex.org/W2373777250","https://openalex.org/W2353956655","https://openalex.org/W2020653254","https://openalex.org/W2010454064","https://openalex.org/W2352072014","https://openalex.org/W217279133","https://openalex.org/W2393487946","https://openalex.org/W2373310108"],"abstract_inverted_index":{"Most":[0],"existing":[1],"buffer":[2,19,34],"insertion":[3],"algorithms,":[4],"such":[5],"as":[6],"van":[7],"Ginneken's":[8],"algorithm,":[9],"consider":[10],"individual":[11],"nets":[12],"and":[13],"therefore":[14],"often":[15],"result":[16],"in":[17,54],"high":[18],"cost":[20],"due":[21],"to":[22,32],"lack":[23],"a":[24],"global":[25],"view.":[26],"Thus,":[27],"circuit-wise":[28,38],"buffering":[29,39],"is":[30],"necessary":[31],"reduce":[33],"cost.":[35],"Recently,":[36],"some":[37],"algorithms":[40,45],"are":[41,46,51],"proposed.":[42],"However,":[43],"these":[44],"based":[47],"on":[48],"heuristics":[49],"which":[50],"not":[52],"scalable":[53],"handling":[55],"large":[56],"circuits.":[57]},"counts_by_year":[{"year":2023,"cited_by_count":1},{"year":2013,"cited_by_count":1},{"year":2012,"cited_by_count":1}],"updated_date":"2026-07-29T14:22:42.915294","created_date":"2025-10-10T00:00:00"}
