{"id":"https://openalex.org/W2082321038","doi":"https://doi.org/10.1145/1391469.1391638","title":"A new paradigm for synthesis and propagation of clock gating conditions","display_name":"A new paradigm for synthesis and propagation of clock gating conditions","publication_year":2008,"publication_date":"2008-06-08","ids":{"openalex":"https://openalex.org/W2082321038","doi":"https://doi.org/10.1145/1391469.1391638","mag":"2082321038"},"language":"en","primary_location":{"id":"doi:10.1145/1391469.1391638","is_oa":false,"landing_page_url":"https://doi.org/10.1145/1391469.1391638","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 45th annual Design Automation Conference","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5082976991","display_name":"Ranan Fraer","orcid":null},"institutions":[{"id":"https://openalex.org/I4210104622","display_name":"Intel (Israel)","ror":"https://ror.org/027t2s119","country_code":"IL","type":"company","lineage":["https://openalex.org/I1343180700","https://openalex.org/I4210104622"]},{"id":"https://openalex.org/I80687555","display_name":"Israel Electric (Israel)","ror":"https://ror.org/01p8dnv11","country_code":"IL","type":"company","lineage":["https://openalex.org/I80687555"]}],"countries":["IL"],"is_corresponding":true,"raw_author_name":"Ranan Fraer","raw_affiliation_strings":["Intel Corporation, Design Technology and Solutions, Haifa, Israel"],"affiliations":[{"raw_affiliation_string":"Intel Corporation, Design Technology and Solutions, Haifa, Israel","institution_ids":["https://openalex.org/I80687555","https://openalex.org/I4210104622"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5032288384","display_name":"Gila Kamhi","orcid":null},"institutions":[{"id":"https://openalex.org/I4210104622","display_name":"Intel (Israel)","ror":"https://ror.org/027t2s119","country_code":"IL","type":"company","lineage":["https://openalex.org/I1343180700","https://openalex.org/I4210104622"]},{"id":"https://openalex.org/I80687555","display_name":"Israel Electric (Israel)","ror":"https://ror.org/01p8dnv11","country_code":"IL","type":"company","lineage":["https://openalex.org/I80687555"]}],"countries":["IL"],"is_corresponding":false,"raw_author_name":"Gila Kamhi","raw_affiliation_strings":["Intel Corporation, Design Technology and Solutions, Haifa, Israel"],"affiliations":[{"raw_affiliation_string":"Intel Corporation, Design Technology and Solutions, Haifa, Israel","institution_ids":["https://openalex.org/I80687555","https://openalex.org/I4210104622"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5089590789","display_name":"Muhammad K. Mhameed","orcid":null},"institutions":[{"id":"https://openalex.org/I80687555","display_name":"Israel Electric (Israel)","ror":"https://ror.org/01p8dnv11","country_code":"IL","type":"company","lineage":["https://openalex.org/I80687555"]},{"id":"https://openalex.org/I4210104622","display_name":"Intel (Israel)","ror":"https://ror.org/027t2s119","country_code":"IL","type":"company","lineage":["https://openalex.org/I1343180700","https://openalex.org/I4210104622"]}],"countries":["IL"],"is_corresponding":false,"raw_author_name":"Muhammad K. Mhameed","raw_affiliation_strings":["Intel Corporation, Design Technology and Solutions, Haifa, Israel"],"affiliations":[{"raw_affiliation_string":"Intel Corporation, Design Technology and Solutions, Haifa, Israel","institution_ids":["https://openalex.org/I80687555","https://openalex.org/I4210104622"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":3,"corresponding_author_ids":["https://openalex.org/A5082976991"],"corresponding_institution_ids":["https://openalex.org/I4210104622","https://openalex.org/I80687555"],"apc_list":null,"apc_paid":null,"fwci":5.3271,"has_fulltext":false,"cited_by_count":35,"citation_normalized_percentile":{"value":0.95649304,"is_in_top_1_percent":false,"is_in_top_10_percent":true},"cited_by_percentile_year":{"min":89,"max":99},"biblio":{"volume":null,"issue":null,"first_page":"658","last_page":"663"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9997000098228455,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/clock-gating","display_name":"Clock gating","score":0.9348673820495605},{"id":"https://openalex.org/keywords/gating","display_name":"Gating","score":0.8186023235321045},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.6383552551269531},{"id":"https://openalex.org/keywords/power-gating","display_name":"Power gating","score":0.603654146194458},{"id":"https://openalex.org/keywords/scalability","display_name":"Scalability","score":0.596798300743103},{"id":"https://openalex.org/keywords/clock-domain-crossing","display_name":"Clock domain crossing","score":0.5882829427719116},{"id":"https://openalex.org/keywords/exploit","display_name":"Exploit","score":0.5151194930076599},{"id":"https://openalex.org/keywords/digital-clock-manager","display_name":"Digital clock manager","score":0.4860847294330597},{"id":"https://openalex.org/keywords/power","display_name":"Power (physics)","score":0.4332540035247803},{"id":"https://openalex.org/keywords/cpu-multiplier","display_name":"CPU multiplier","score":0.42617395520210266},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.4097733497619629},{"id":"https://openalex.org/keywords/clock-skew","display_name":"Clock skew","score":0.3828059434890747},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.34454187750816345},{"id":"https://openalex.org/keywords/synchronous-circuit","display_name":"Synchronous circuit","score":0.2920154929161072},{"id":"https://openalex.org/keywords/clock-signal","display_name":"Clock signal","score":0.25037863850593567},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.15551581978797913},{"id":"https://openalex.org/keywords/transistor","display_name":"Transistor","score":0.1462244689464569},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.11018610000610352},{"id":"https://openalex.org/keywords/jitter","display_name":"Jitter","score":0.09807032346725464},{"id":"https://openalex.org/keywords/telecommunications","display_name":"Telecommunications","score":0.09212204813957214},{"id":"https://openalex.org/keywords/physics","display_name":"Physics","score":0.08851656317710876}],"concepts":[{"id":"https://openalex.org/C22716491","wikidata":"https://www.wikidata.org/wiki/Q590170","display_name":"Clock gating","level":5,"score":0.9348673820495605},{"id":"https://openalex.org/C194544171","wikidata":"https://www.wikidata.org/wiki/Q21105679","display_name":"Gating","level":2,"score":0.8186023235321045},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6383552551269531},{"id":"https://openalex.org/C2780700455","wikidata":"https://www.wikidata.org/wiki/Q7236515","display_name":"Power gating","level":4,"score":0.603654146194458},{"id":"https://openalex.org/C48044578","wikidata":"https://www.wikidata.org/wiki/Q727490","display_name":"Scalability","level":2,"score":0.596798300743103},{"id":"https://openalex.org/C127204226","wikidata":"https://www.wikidata.org/wiki/Q5134799","display_name":"Clock domain crossing","level":5,"score":0.5882829427719116},{"id":"https://openalex.org/C165696696","wikidata":"https://www.wikidata.org/wiki/Q11287","display_name":"Exploit","level":2,"score":0.5151194930076599},{"id":"https://openalex.org/C113074038","wikidata":"https://www.wikidata.org/wiki/Q5276052","display_name":"Digital clock manager","level":5,"score":0.4860847294330597},{"id":"https://openalex.org/C163258240","wikidata":"https://www.wikidata.org/wiki/Q25342","display_name":"Power (physics)","level":2,"score":0.4332540035247803},{"id":"https://openalex.org/C125576049","wikidata":"https://www.wikidata.org/wiki/Q2246273","display_name":"CPU multiplier","level":5,"score":0.42617395520210266},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.4097733497619629},{"id":"https://openalex.org/C60501442","wikidata":"https://www.wikidata.org/wiki/Q4382014","display_name":"Clock skew","level":4,"score":0.3828059434890747},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.34454187750816345},{"id":"https://openalex.org/C42196554","wikidata":"https://www.wikidata.org/wiki/Q1186179","display_name":"Synchronous circuit","level":4,"score":0.2920154929161072},{"id":"https://openalex.org/C137059387","wikidata":"https://www.wikidata.org/wiki/Q426882","display_name":"Clock signal","level":3,"score":0.25037863850593567},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.15551581978797913},{"id":"https://openalex.org/C172385210","wikidata":"https://www.wikidata.org/wiki/Q5339","display_name":"Transistor","level":3,"score":0.1462244689464569},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.11018610000610352},{"id":"https://openalex.org/C134652429","wikidata":"https://www.wikidata.org/wiki/Q1052698","display_name":"Jitter","level":2,"score":0.09807032346725464},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.09212204813957214},{"id":"https://openalex.org/C121332964","wikidata":"https://www.wikidata.org/wiki/Q413","display_name":"Physics","level":0,"score":0.08851656317710876},{"id":"https://openalex.org/C38652104","wikidata":"https://www.wikidata.org/wiki/Q3510521","display_name":"Computer security","level":1,"score":0.0},{"id":"https://openalex.org/C165801399","wikidata":"https://www.wikidata.org/wiki/Q25428","display_name":"Voltage","level":2,"score":0.0},{"id":"https://openalex.org/C77088390","wikidata":"https://www.wikidata.org/wiki/Q8513","display_name":"Database","level":1,"score":0.0},{"id":"https://openalex.org/C62520636","wikidata":"https://www.wikidata.org/wiki/Q944","display_name":"Quantum mechanics","level":1,"score":0.0},{"id":"https://openalex.org/C42407357","wikidata":"https://www.wikidata.org/wiki/Q521","display_name":"Physiology","level":1,"score":0.0},{"id":"https://openalex.org/C86803240","wikidata":"https://www.wikidata.org/wiki/Q420","display_name":"Biology","level":0,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1145/1391469.1391638","is_oa":false,"landing_page_url":"https://doi.org/10.1145/1391469.1391638","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 45th annual Design Automation Conference","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"score":0.8199999928474426,"id":"https://metadata.un.org/sdg/7","display_name":"Affordable and clean energy"}],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":7,"referenced_works":["https://openalex.org/W1996445094","https://openalex.org/W2114394884","https://openalex.org/W2115283580","https://openalex.org/W2119765938","https://openalex.org/W2137310043","https://openalex.org/W2152938140","https://openalex.org/W3193564476"],"related_works":["https://openalex.org/W2088914741","https://openalex.org/W4247180033","https://openalex.org/W2040807843","https://openalex.org/W2559451387","https://openalex.org/W2495024767","https://openalex.org/W3006003651","https://openalex.org/W4249038728","https://openalex.org/W2474747038","https://openalex.org/W4313332229","https://openalex.org/W2557143395"],"abstract_inverted_index":{"Clock":[0],"gating":[1,39,45,92],"has":[2],"become":[3],"a":[4,65,80],"standard":[5],"practice":[6],"for":[7,47,74,90],"saving":[8],"dynamic":[9],"power":[10,101],"in":[11,40],"the":[12,36,104,111],"clock":[13,30,38,75,112],"network.":[14],"Due":[15],"to":[16,22,34,42,70],"design":[17],"reuse,":[18],"it":[19],"is":[20,64],"common":[21],"find":[23],"designs":[24],"that":[25,49],"have":[26],"already":[27],"some":[28],"partial":[29],"gating.":[31,76],"We":[32],"propose":[33],"exploit":[35],"existing":[37],"order":[41],"extract":[43,71],"stronger":[44],"conditions":[46,73,93],"blocks":[48],"are":[50],"poorly":[51],"gated":[52,55],"or":[53],"not":[54],"at":[56],"all.":[57],"A":[58],"second":[59],"contribution":[60],"of":[61,83,106,110],"our":[62],"paper":[63],"robust":[66],"and":[67,85,95],"scalable":[68],"approach":[69],"stability":[72,86],"Finally,":[77],"we":[78],"present":[79],"uniform":[81],"treatment":[82],"unobservability":[84],"as":[87],"dual":[88],"approaches":[89],"propagating":[91],"forward":[94],"backward.":[96],"Experimental":[97],"results":[98],"demonstrate":[99],"significant":[100],"reduction":[102],"(in":[103],"range":[105],"14%":[107],"--":[108],"55%":[109],"power)":[113],"on":[114],"Intel":[115],"micro-processor":[116],"designs.":[117]},"counts_by_year":[{"year":2021,"cited_by_count":1},{"year":2019,"cited_by_count":2},{"year":2018,"cited_by_count":1},{"year":2017,"cited_by_count":3},{"year":2016,"cited_by_count":1},{"year":2015,"cited_by_count":6},{"year":2013,"cited_by_count":1},{"year":2012,"cited_by_count":4}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}