{"id":"https://openalex.org/W2109343975","doi":"https://doi.org/10.1145/1391469.1391623","title":"Multiobjective optimization of sleep vector for zigzag power-gated circuits in standard cell elements","display_name":"Multiobjective optimization of sleep vector for zigzag power-gated circuits in standard cell elements","publication_year":2008,"publication_date":"2008-06-08","ids":{"openalex":"https://openalex.org/W2109343975","doi":"https://doi.org/10.1145/1391469.1391623","mag":"2109343975"},"language":"en","primary_location":{"id":"doi:10.1145/1391469.1391623","is_oa":false,"landing_page_url":"https://doi.org/10.1145/1391469.1391623","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 45th annual Design Automation Conference","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5108744170","display_name":"Seungwhun Paik","orcid":null},"institutions":[{"id":"https://openalex.org/I157485424","display_name":"Korea Advanced Institute of Science and Technology","ror":"https://ror.org/05apxxy63","country_code":"KR","type":"education","lineage":["https://openalex.org/I157485424"]}],"countries":["KR"],"is_corresponding":false,"raw_author_name":"Seungwhun Paik","raw_affiliation_strings":["KAIST, Daejeon, Korea","Dept. of Electr. Eng., KAIST, Daejeon#TAB#"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"KAIST, Daejeon, Korea","institution_ids":["https://openalex.org/I157485424"]},{"raw_affiliation_string":"Dept. of Electr. Eng., KAIST, Daejeon#TAB#","institution_ids":["https://openalex.org/I157485424"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5020011072","display_name":"Youngsoo Shin","orcid":"https://orcid.org/0000-0002-7474-9212"},"institutions":[{"id":"https://openalex.org/I157485424","display_name":"Korea Advanced Institute of Science and Technology","ror":"https://ror.org/05apxxy63","country_code":"KR","type":"education","lineage":["https://openalex.org/I157485424"]}],"countries":["KR"],"is_corresponding":false,"raw_author_name":"Youngsoo Shin","raw_affiliation_strings":["KAIST, Daejeon, Korea","Dept. of Electr. Eng., KAIST, Daejeon#TAB#"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"KAIST, Daejeon, Korea","institution_ids":["https://openalex.org/I157485424"]},{"raw_affiliation_string":"Dept. of Electr. Eng., KAIST, Daejeon#TAB#","institution_ids":["https://openalex.org/I157485424"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":2,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":0.3392,"has_fulltext":false,"cited_by_count":2,"citation_normalized_percentile":{"value":0.65486695,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":90,"max":94},"biblio":{"volume":null,"issue":null,"first_page":"600","last_page":"605"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9997000098228455,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9973000288009644,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/power-gating","display_name":"Power gating","score":0.9115151166915894},{"id":"https://openalex.org/keywords/sleep-mode","display_name":"Sleep mode","score":0.7970414161682129},{"id":"https://openalex.org/keywords/standby-power","display_name":"Standby power","score":0.6670033931732178},{"id":"https://openalex.org/keywords/electronic-circuit","display_name":"Electronic circuit","score":0.6356194615364075},{"id":"https://openalex.org/keywords/pmos-logic","display_name":"PMOS logic","score":0.6109311580657959},{"id":"https://openalex.org/keywords/zigzag","display_name":"Zigzag","score":0.5727738738059998},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.5322767496109009},{"id":"https://openalex.org/keywords/benchmark","display_name":"Benchmark (surveying)","score":0.5121581554412842},{"id":"https://openalex.org/keywords/nmos-logic","display_name":"NMOS logic","score":0.43858441710472107},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.4175987243652344},{"id":"https://openalex.org/keywords/power","display_name":"Power (physics)","score":0.4119737148284912},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.3335146903991699},{"id":"https://openalex.org/keywords/transistor","display_name":"Transistor","score":0.2593500018119812},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.21633407473564148},{"id":"https://openalex.org/keywords/mathematics","display_name":"Mathematics","score":0.16087639331817627},{"id":"https://openalex.org/keywords/voltage","display_name":"Voltage","score":0.1165219247341156}],"concepts":[{"id":"https://openalex.org/C2780700455","wikidata":"https://www.wikidata.org/wiki/Q7236515","display_name":"Power gating","level":4,"score":0.9115151166915894},{"id":"https://openalex.org/C57149124","wikidata":"https://www.wikidata.org/wiki/Q587346","display_name":"Sleep mode","level":4,"score":0.7970414161682129},{"id":"https://openalex.org/C7140552","wikidata":"https://www.wikidata.org/wiki/Q1366402","display_name":"Standby power","level":3,"score":0.6670033931732178},{"id":"https://openalex.org/C134146338","wikidata":"https://www.wikidata.org/wiki/Q1815901","display_name":"Electronic circuit","level":2,"score":0.6356194615364075},{"id":"https://openalex.org/C27050352","wikidata":"https://www.wikidata.org/wiki/Q173605","display_name":"PMOS logic","level":4,"score":0.6109311580657959},{"id":"https://openalex.org/C192271897","wikidata":"https://www.wikidata.org/wiki/Q198438","display_name":"Zigzag","level":2,"score":0.5727738738059998},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.5322767496109009},{"id":"https://openalex.org/C185798385","wikidata":"https://www.wikidata.org/wiki/Q1161707","display_name":"Benchmark (surveying)","level":2,"score":0.5121581554412842},{"id":"https://openalex.org/C197162436","wikidata":"https://www.wikidata.org/wiki/Q83908","display_name":"NMOS logic","level":4,"score":0.43858441710472107},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.4175987243652344},{"id":"https://openalex.org/C163258240","wikidata":"https://www.wikidata.org/wiki/Q25342","display_name":"Power (physics)","level":2,"score":0.4119737148284912},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.3335146903991699},{"id":"https://openalex.org/C172385210","wikidata":"https://www.wikidata.org/wiki/Q5339","display_name":"Transistor","level":3,"score":0.2593500018119812},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.21633407473564148},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.16087639331817627},{"id":"https://openalex.org/C165801399","wikidata":"https://www.wikidata.org/wiki/Q25428","display_name":"Voltage","level":2,"score":0.1165219247341156},{"id":"https://openalex.org/C62520636","wikidata":"https://www.wikidata.org/wiki/Q944","display_name":"Quantum mechanics","level":1,"score":0.0},{"id":"https://openalex.org/C121332964","wikidata":"https://www.wikidata.org/wiki/Q413","display_name":"Physics","level":0,"score":0.0},{"id":"https://openalex.org/C205649164","wikidata":"https://www.wikidata.org/wiki/Q1071","display_name":"Geography","level":0,"score":0.0},{"id":"https://openalex.org/C2984118289","wikidata":"https://www.wikidata.org/wiki/Q29954","display_name":"Power consumption","level":3,"score":0.0},{"id":"https://openalex.org/C13280743","wikidata":"https://www.wikidata.org/wiki/Q131089","display_name":"Geodesy","level":1,"score":0.0},{"id":"https://openalex.org/C2524010","wikidata":"https://www.wikidata.org/wiki/Q8087","display_name":"Geometry","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1145/1391469.1391623","is_oa":false,"landing_page_url":"https://doi.org/10.1145/1391469.1391623","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 45th annual Design Automation Conference","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"id":"https://metadata.un.org/sdg/7","display_name":"Affordable and clean energy","score":0.8999999761581421}],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":14,"referenced_works":["https://openalex.org/W1503103436","https://openalex.org/W1535830875","https://openalex.org/W2017370932","https://openalex.org/W2106157873","https://openalex.org/W2114621701","https://openalex.org/W2121225064","https://openalex.org/W2126105956","https://openalex.org/W2139542266","https://openalex.org/W2143727503","https://openalex.org/W2145267773","https://openalex.org/W2168075227","https://openalex.org/W2169033838","https://openalex.org/W2173522374","https://openalex.org/W6678175888"],"related_works":["https://openalex.org/W4386261925","https://openalex.org/W2048420745","https://openalex.org/W2082944690","https://openalex.org/W2263373136","https://openalex.org/W1914349328","https://openalex.org/W2160067645","https://openalex.org/W2023334077","https://openalex.org/W2005494397","https://openalex.org/W2012065800","https://openalex.org/W2127275249"],"abstract_inverted_index":{"Zigzag":[0],"power":[1,12,24,35,59,80,93,114],"gating":[2,13,25],"(ZPG)":[3],"has":[4,49],"been":[5],"proposed":[6],"to":[7,26,38,53,88,98,120,187],"alleviate":[8],"the":[9,21,39,72,100,148,158],"drawback":[10],"of":[11,23,41,58,64,74,160],"in":[14,46,162,167,175],"its":[15,51],"long":[16],"wake-up":[17],"delay,":[18],"thereby":[19],"broadening":[20],"application":[22,52],"suppressing":[27],"active-":[28],"as":[29,31,135],"well":[30],"standby-leakage.":[32],"However,":[33],"complicated":[34],"network":[36,115],"due":[37],"use":[40,57,73,121],"nMOS":[42],"and":[43,66,85,143,165,191],"pMOS":[44],"switches":[45],"zigzag":[47],"fashion":[48],"limited":[50],"custom":[54],"circuits.":[55,129],"Heterogeneous":[56],"rails":[60],"inevitably":[61],"incurs":[62],"overhead":[63],"area":[65],"wirelength":[67],"during":[68],"physical":[69],"design.":[70],"Furthermore,":[71],"sleep":[75,133],"vector":[76,134],"causes":[77],"additional":[78],"switching":[79,92],"when":[81],"entering":[82],"standby":[83],"mode":[84],"returning":[86],"back":[87],"active":[89],"mode.":[90],"The":[91,178],"should":[94],"be":[95],"minimized":[96],"not":[97],"outweigh":[99],"leakage":[101],"saving":[102,159],"by":[103,150],"employing":[104,151],"ZPG":[105,128],"scheme.":[106],"In":[107],"this":[108],"paper,":[109],"we":[110],"propose":[111],"a":[112,136],"complete":[113,179],"architecture,":[116],"which":[117],"allows":[118],"us":[119],"unmodified":[122],"standard":[123],"cell":[124],"elements":[125],"for":[126,171],"implementing":[127],"We":[130,146],"formulate":[131],"selecting":[132],"multi-objective":[137],"optimization":[138],"problem,":[139],"minimizing":[140],"transition":[141,163],"energy":[142,164],"total":[144],"wirelength.":[145],"solve":[147],"problem":[149],"multiobjective":[152],"genetic-based":[153],"algorithm.":[154],"Experimental":[155],"results":[156],"show":[157],"39%":[161],"8%":[166],"wirelength,":[168],"on":[169],"average,":[170],"several":[172],"benchmark":[173],"circuits":[174],"65-nm":[176,194],"technology.":[177,195],"design":[180],"flow":[181],"starting":[182],"from":[183],"RTL":[184],"description":[185],"down":[186],"layout":[188],"is":[189],"proposed,":[190],"assessed":[192],"with":[193]},"counts_by_year":[{"year":2012,"cited_by_count":1}],"updated_date":"2026-06-11T09:08:48.828518","created_date":"2025-10-10T00:00:00"}
