{"id":"https://openalex.org/W2156974682","doi":"https://doi.org/10.1145/1391469.1391511","title":"Application-driven floorplan-aware voltage island design","display_name":"Application-driven floorplan-aware voltage island design","publication_year":2008,"publication_date":"2008-06-08","ids":{"openalex":"https://openalex.org/W2156974682","doi":"https://doi.org/10.1145/1391469.1391511","mag":"2156974682"},"language":"en","primary_location":{"id":"doi:10.1145/1391469.1391511","is_oa":false,"landing_page_url":"https://doi.org/10.1145/1391469.1391511","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 45th annual Design Automation Conference","raw_type":"proceedings-article"},"type":"conference-paper","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5084943434","display_name":"Dipanjan Sengupta","orcid":null},"institutions":[{"id":"https://openalex.org/I141945490","display_name":"University of British Columbia","ror":"https://ror.org/03rmrcq20","country_code":"CA","type":"education","lineage":["https://openalex.org/I141945490"]}],"countries":["CA"],"is_corresponding":false,"raw_author_name":"Dipanjan Sengupta","raw_affiliation_strings":["University of British Columbia, Vancouver, Canada"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"University of British Columbia, Vancouver, Canada","institution_ids":["https://openalex.org/I141945490"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5111377679","display_name":"Resve Saleh","orcid":null},"institutions":[{"id":"https://openalex.org/I141945490","display_name":"University of British Columbia","ror":"https://ror.org/03rmrcq20","country_code":"CA","type":"education","lineage":["https://openalex.org/I141945490"]}],"countries":["CA"],"is_corresponding":false,"raw_author_name":"Resve Saleh","raw_affiliation_strings":["University of British Columbia, Vancouver, Canada"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"University of British Columbia, Vancouver, Canada","institution_ids":["https://openalex.org/I141945490"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":1,"corresponding_author_ids":[],"corresponding_institution_ids":["https://openalex.org/I141945490"],"apc_list":null,"apc_paid":null,"fwci":7.1165,"has_fulltext":false,"cited_by_count":28,"citation_normalized_percentile":{"value":0.98125466,"is_in_top_1_percent":false,"is_in_top_10_percent":true},"cited_by_percentile_year":{"min":89,"max":99},"biblio":{"volume":null,"issue":null,"first_page":"155","last_page":"160"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9987999796867371,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/floorplan","display_name":"Floorplan","score":0.9815632104873657},{"id":"https://openalex.org/keywords/voltage","display_name":"Voltage","score":0.6395865678787231},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.6288566589355469},{"id":"https://openalex.org/keywords/integrated-circuit-layout","display_name":"Integrated circuit layout","score":0.5508058071136475},{"id":"https://openalex.org/keywords/chip","display_name":"Chip","score":0.46698328852653503},{"id":"https://openalex.org/keywords/reduction","display_name":"Reduction (mathematics)","score":0.46697258949279785},{"id":"https://openalex.org/keywords/partition","display_name":"Partition (number theory)","score":0.4569862186908722},{"id":"https://openalex.org/keywords/system-on-a-chip","display_name":"System on a chip","score":0.42502692341804504},{"id":"https://openalex.org/keywords/power","display_name":"Power (physics)","score":0.4157140254974365},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.3575088381767273},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.3282957673072815},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.3247557282447815},{"id":"https://openalex.org/keywords/integrated-circuit","display_name":"Integrated circuit","score":0.272276371717453},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.25187891721725464},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.15073361992835999},{"id":"https://openalex.org/keywords/telecommunications","display_name":"Telecommunications","score":0.07505032420158386}],"concepts":[{"id":"https://openalex.org/C130145326","wikidata":"https://www.wikidata.org/wiki/Q1553985","display_name":"Floorplan","level":2,"score":0.9815632104873657},{"id":"https://openalex.org/C165801399","wikidata":"https://www.wikidata.org/wiki/Q25428","display_name":"Voltage","level":2,"score":0.6395865678787231},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6288566589355469},{"id":"https://openalex.org/C2765594","wikidata":"https://www.wikidata.org/wiki/Q2624187","display_name":"Integrated circuit layout","level":3,"score":0.5508058071136475},{"id":"https://openalex.org/C165005293","wikidata":"https://www.wikidata.org/wiki/Q1074500","display_name":"Chip","level":2,"score":0.46698328852653503},{"id":"https://openalex.org/C111335779","wikidata":"https://www.wikidata.org/wiki/Q3454686","display_name":"Reduction (mathematics)","level":2,"score":0.46697258949279785},{"id":"https://openalex.org/C42812","wikidata":"https://www.wikidata.org/wiki/Q1082910","display_name":"Partition (number theory)","level":2,"score":0.4569862186908722},{"id":"https://openalex.org/C118021083","wikidata":"https://www.wikidata.org/wiki/Q610398","display_name":"System on a chip","level":2,"score":0.42502692341804504},{"id":"https://openalex.org/C163258240","wikidata":"https://www.wikidata.org/wiki/Q25342","display_name":"Power (physics)","level":2,"score":0.4157140254974365},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.3575088381767273},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.3282957673072815},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.3247557282447815},{"id":"https://openalex.org/C530198007","wikidata":"https://www.wikidata.org/wiki/Q80831","display_name":"Integrated circuit","level":2,"score":0.272276371717453},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.25187891721725464},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.15073361992835999},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.07505032420158386},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.0},{"id":"https://openalex.org/C121332964","wikidata":"https://www.wikidata.org/wiki/Q413","display_name":"Physics","level":0,"score":0.0},{"id":"https://openalex.org/C2524010","wikidata":"https://www.wikidata.org/wiki/Q8087","display_name":"Geometry","level":1,"score":0.0},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.0},{"id":"https://openalex.org/C114614502","wikidata":"https://www.wikidata.org/wiki/Q76592","display_name":"Combinatorics","level":1,"score":0.0},{"id":"https://openalex.org/C62520636","wikidata":"https://www.wikidata.org/wiki/Q944","display_name":"Quantum mechanics","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1145/1391469.1391511","is_oa":false,"landing_page_url":"https://doi.org/10.1145/1391469.1391511","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 45th annual Design Automation Conference","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":18,"referenced_works":["https://openalex.org/W1862367345","https://openalex.org/W1967800299","https://openalex.org/W2007916227","https://openalex.org/W2015033143","https://openalex.org/W2073092303","https://openalex.org/W2082348718","https://openalex.org/W2098143668","https://openalex.org/W2104771005","https://openalex.org/W2106319297","https://openalex.org/W2124472440","https://openalex.org/W2129021906","https://openalex.org/W2139524433","https://openalex.org/W2142386205","https://openalex.org/W2148698121","https://openalex.org/W2163632212","https://openalex.org/W2168300107","https://openalex.org/W2168908650","https://openalex.org/W6675730974"],"related_works":["https://openalex.org/W4400482493","https://openalex.org/W2124495928","https://openalex.org/W2096129555","https://openalex.org/W2097517502","https://openalex.org/W2129355781","https://openalex.org/W4363620137","https://openalex.org/W2161137937","https://openalex.org/W4233404530","https://openalex.org/W2052733504","https://openalex.org/W2152479836"],"abstract_inverted_index":{"Among":[0],"the":[1,12,23,35,40,57,70,75,101,107,113,126],"different":[2,24],"methods":[3],"of":[4,59,112,161],"reducing":[5,60],"power":[6,145],"for":[7,78],"core-based":[8],"system-on-chip":[9],"(SoC)":[10],"designs,":[11],"voltage":[13,32,51,71,79,92],"island":[14,54,80],"technique":[15,88],"has":[16],"gained":[17],"in":[18,39,119,128,144,149],"popularity.":[19],"Assigning":[20],"cores":[21,102],"to":[22,29,50,89,125,137],"supply":[25],"voltages":[26],"and":[27,53,65,115,146],"floorplanning":[28],"create":[30],"contiguous":[31],"islands":[33],"are":[34,123,151],"two":[36],"important":[37],"steps":[38],"design":[41],"process.":[42],"We":[43],"propose":[44],"a":[45,87,91,131,141],"new":[46],"application-driven,":[47],"floorplan-aware":[48],"approach":[49],"partitioning":[52],"creation":[55],"with":[56,156],"objective":[58],"overall":[61],"SoC":[62],"power,":[63],"area":[64,150],"runtime.":[66],"Previous":[67],"approaches":[68],"used":[69,118],"assignment":[72,93],"table":[73,94],"as":[74],"starting":[76],"point":[77],"creation.":[81],"In":[82],"this":[83],"paper,":[84],"we":[85,99],"present":[86],"generate":[90],"using":[95,153],"dynamic":[96],"programming.":[97],"Next,":[98],"partition":[100],"into":[103],"islands,":[104],"based":[105],"on":[106],"Power":[108],"State":[109],"Model":[110],"(PSM)":[111],"application,":[114],"connectivity":[116],"information":[117],"floorplanning.":[120],"Finally,":[121],"solutions":[122],"sent":[124],"floorplanner":[127],"sequence":[129],"until":[130],"valid":[132],"solution":[133],"is":[134],"reached.":[135],"Compared":[136],"previously":[138],"reported":[139],"techniques,":[140],"10%":[142],"reduction":[143,148],"8%":[147],"achieved":[152],"our":[154],"approach,":[155],"an":[157],"average":[158],"runtime":[159],"improvement":[160],"2.3X.":[162]},"counts_by_year":[{"year":2021,"cited_by_count":1},{"year":2017,"cited_by_count":2},{"year":2015,"cited_by_count":1},{"year":2014,"cited_by_count":2},{"year":2013,"cited_by_count":1},{"year":2012,"cited_by_count":6}],"updated_date":"2026-07-29T14:22:42.915294","created_date":"2025-10-10T00:00:00"}