{"id":"https://openalex.org/W2104262876","doi":"https://doi.org/10.1145/1391469.1391497","title":"A MIPS R2000 implementation","display_name":"A MIPS R2000 implementation","publication_year":2008,"publication_date":"2008-06-08","ids":{"openalex":"https://openalex.org/W2104262876","doi":"https://doi.org/10.1145/1391469.1391497","mag":"2104262876"},"language":"en","primary_location":{"id":"doi:10.1145/1391469.1391497","is_oa":false,"landing_page_url":"https://doi.org/10.1145/1391469.1391497","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 45th annual Design Automation Conference","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5050270997","display_name":"Nathaniel Pinckney","orcid":"https://orcid.org/0000-0001-6159-8964"},"institutions":[{"id":"https://openalex.org/I133543626","display_name":"Harvey Mudd College","ror":"https://ror.org/025ecfn45","country_code":"US","type":"education","lineage":["https://openalex.org/I133543626"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Nathaniel Pinckney","raw_affiliation_strings":["Harvey Mudd College, Claremont, CA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Harvey Mudd College, Claremont, CA","institution_ids":["https://openalex.org/I133543626"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5085919571","display_name":"Thomas W. Barr","orcid":null},"institutions":[{"id":"https://openalex.org/I133543626","display_name":"Harvey Mudd College","ror":"https://ror.org/025ecfn45","country_code":"US","type":"education","lineage":["https://openalex.org/I133543626"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Thomas Barr","raw_affiliation_strings":["Harvey Mudd College, Claremont, CA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Harvey Mudd College, Claremont, CA","institution_ids":["https://openalex.org/I133543626"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5019897514","display_name":"Michael Dayringer","orcid":null},"institutions":[{"id":"https://openalex.org/I133543626","display_name":"Harvey Mudd College","ror":"https://ror.org/025ecfn45","country_code":"US","type":"education","lineage":["https://openalex.org/I133543626"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Michael Dayringer","raw_affiliation_strings":["Harvey Mudd College, Claremont, CA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Harvey Mudd College, Claremont, CA","institution_ids":["https://openalex.org/I133543626"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5069328843","display_name":"Matthew McKnett","orcid":null},"institutions":[{"id":"https://openalex.org/I133543626","display_name":"Harvey Mudd College","ror":"https://ror.org/025ecfn45","country_code":"US","type":"education","lineage":["https://openalex.org/I133543626"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Matthew McKnett","raw_affiliation_strings":["Harvey Mudd College, Claremont, CA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Harvey Mudd College, Claremont, CA","institution_ids":["https://openalex.org/I133543626"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5112858111","display_name":"Nan Jiang","orcid":"https://orcid.org/0000-0001-7895-8989"},"institutions":[{"id":"https://openalex.org/I133543626","display_name":"Harvey Mudd College","ror":"https://ror.org/025ecfn45","country_code":"US","type":"education","lineage":["https://openalex.org/I133543626"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Nan Jiang","raw_affiliation_strings":["Harvey Mudd College, Claremont, CA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Harvey Mudd College, Claremont, CA","institution_ids":["https://openalex.org/I133543626"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5079393311","display_name":"Carl Nygaard","orcid":null},"institutions":[{"id":"https://openalex.org/I133543626","display_name":"Harvey Mudd College","ror":"https://ror.org/025ecfn45","country_code":"US","type":"education","lineage":["https://openalex.org/I133543626"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Carl Nygaard","raw_affiliation_strings":["Harvey Mudd College, Claremont, CA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Harvey Mudd College, Claremont, CA","institution_ids":["https://openalex.org/I133543626"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5101661944","display_name":"David Harris","orcid":"https://orcid.org/0000-0001-9075-5965"},"institutions":[{"id":"https://openalex.org/I133543626","display_name":"Harvey Mudd College","ror":"https://ror.org/025ecfn45","country_code":"US","type":"education","lineage":["https://openalex.org/I133543626"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"David Money Harris","raw_affiliation_strings":["Harvey Mudd College, Claremont, CA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Harvey Mudd College, Claremont, CA","institution_ids":["https://openalex.org/I133543626"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5086069450","display_name":"Joel Stanley","orcid":null},"institutions":[{"id":"https://openalex.org/I5681781","display_name":"The University of Adelaide","ror":"https://ror.org/00892tw58","country_code":"AU","type":"education","lineage":["https://openalex.org/I5681781"]}],"countries":["AU"],"is_corresponding":false,"raw_author_name":"Joel Stanley","raw_affiliation_strings":["The University of Adelaide, SA, Australia","The University of Adelaide, SA, Australia#TAB#"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"The University of Adelaide, SA, Australia","institution_ids":["https://openalex.org/I5681781"]},{"raw_affiliation_string":"The University of Adelaide, SA, Australia#TAB#","institution_ids":["https://openalex.org/I5681781"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5073440359","display_name":"Braden J. Phillips","orcid":"https://orcid.org/0000-0001-8288-4791"},"institutions":[{"id":"https://openalex.org/I5681781","display_name":"The University of Adelaide","ror":"https://ror.org/00892tw58","country_code":"AU","type":"education","lineage":["https://openalex.org/I5681781"]}],"countries":["AU"],"is_corresponding":false,"raw_author_name":"Braden Phillips","raw_affiliation_strings":["The University of Adelaide, SA, Australia","The University of Adelaide, SA, Australia#TAB#"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"The University of Adelaide, SA, Australia","institution_ids":["https://openalex.org/I5681781"]},{"raw_affiliation_string":"The University of Adelaide, SA, Australia#TAB#","institution_ids":["https://openalex.org/I5681781"]}]}],"institutions":[],"countries_distinct_count":2,"institutions_distinct_count":9,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":2.0719,"has_fulltext":false,"cited_by_count":13,"citation_normalized_percentile":{"value":0.88131752,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":90,"max":97},"biblio":{"volume":null,"issue":null,"first_page":"102","last_page":"107"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9994000196456909,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9994000196456909,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.9990000128746033,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9980999827384949,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/schematic","display_name":"Schematic","score":0.7212095260620117},{"id":"https://openalex.org/keywords/verilog","display_name":"Verilog","score":0.7128125429153442},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7012721300125122},{"id":"https://openalex.org/keywords/very-large-scale-integration","display_name":"Very-large-scale integration","score":0.6825724840164185},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.5887039303779602},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.4957602918148041},{"id":"https://openalex.org/keywords/cmos","display_name":"CMOS","score":0.4739561080932617},{"id":"https://openalex.org/keywords/application-specific-integrated-circuit","display_name":"Application-specific integrated circuit","score":0.45586562156677246},{"id":"https://openalex.org/keywords/process","display_name":"Process (computing)","score":0.4395800828933716},{"id":"https://openalex.org/keywords/microarchitecture","display_name":"Microarchitecture","score":0.4291667640209198},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.3900147080421448},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.2248782217502594},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.1619938611984253},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.14521178603172302},{"id":"https://openalex.org/keywords/operating-system","display_name":"Operating system","score":0.12381649017333984}],"concepts":[{"id":"https://openalex.org/C192328126","wikidata":"https://www.wikidata.org/wiki/Q4514647","display_name":"Schematic","level":2,"score":0.7212095260620117},{"id":"https://openalex.org/C2779030575","wikidata":"https://www.wikidata.org/wiki/Q827773","display_name":"Verilog","level":3,"score":0.7128125429153442},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7012721300125122},{"id":"https://openalex.org/C14580979","wikidata":"https://www.wikidata.org/wiki/Q876049","display_name":"Very-large-scale integration","level":2,"score":0.6825724840164185},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.5887039303779602},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.4957602918148041},{"id":"https://openalex.org/C46362747","wikidata":"https://www.wikidata.org/wiki/Q173431","display_name":"CMOS","level":2,"score":0.4739561080932617},{"id":"https://openalex.org/C77390884","wikidata":"https://www.wikidata.org/wiki/Q217302","display_name":"Application-specific integrated circuit","level":2,"score":0.45586562156677246},{"id":"https://openalex.org/C98045186","wikidata":"https://www.wikidata.org/wiki/Q205663","display_name":"Process (computing)","level":2,"score":0.4395800828933716},{"id":"https://openalex.org/C107598950","wikidata":"https://www.wikidata.org/wiki/Q259864","display_name":"Microarchitecture","level":2,"score":0.4291667640209198},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.3900147080421448},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.2248782217502594},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.1619938611984253},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.14521178603172302},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.12381649017333984}],"mesh":[],"locations_count":2,"locations":[{"id":"doi:10.1145/1391469.1391497","is_oa":false,"landing_page_url":"https://doi.org/10.1145/1391469.1391497","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 45th annual Design Automation Conference","raw_type":"proceedings-article"},{"id":"pmh:oai:CiteSeerX.psu:10.1.1.159.283","is_oa":false,"landing_page_url":"http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.159.283","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"http://www3.hmc.edu/~harris/research/mipsstudentdesign08.pdf","raw_type":"text"}],"best_oa_location":null,"sustainable_development_goals":[{"score":0.5299999713897705,"id":"https://metadata.un.org/sdg/9","display_name":"Industry, innovation and infrastructure"}],"awards":[],"funders":[{"id":"https://openalex.org/F4320309332","display_name":"Harvey Mudd College","ror":"https://ror.org/025ecfn45"},{"id":"https://openalex.org/F4320310179","display_name":"University of Oklahoma","ror":"https://ror.org/02aqsxs83"},{"id":"https://openalex.org/F4320320978","display_name":"University of Adelaide","ror":"https://ror.org/00892tw58"}],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":2,"referenced_works":["https://openalex.org/W1969660388","https://openalex.org/W2143795231"],"related_works":["https://openalex.org/W3154683910","https://openalex.org/W1846734616","https://openalex.org/W2359532622","https://openalex.org/W3134543635","https://openalex.org/W2921318524","https://openalex.org/W2377571686","https://openalex.org/W4380988671","https://openalex.org/W2117342402","https://openalex.org/W2128735135","https://openalex.org/W1663661117"],"abstract_inverted_index":{"Thirty-four":[0],"undergraduates":[1],"implemented":[2],"a":[3,17,31],"MIPS":[4],"R2000":[5],"processor":[6,42],"for":[7],"an":[8,48],"introductory":[9],"CMOS":[10],"VLSI":[11],"design":[12],"course.":[13],"This":[14],"included":[15,52],"designing":[16],"microarchitecture":[18],"in":[19],"Verilog,":[20],"developing":[21],"custom":[22],"PLA":[23],"generation":[24],"and":[25,37,55],"ad-hoc":[26],"random":[27],"testing":[28],"tools,":[29],"creating":[30],"standard":[32],"cell":[33],"library,":[34],"schematics,":[35],"layout,":[36],"PCB":[38],"test":[39],"board.":[40],"The":[41],"was":[43],"fabricated":[44],"by":[45],"MOSIS":[46],"on":[47],"AMI":[49],"0.5-micron":[50],"process,":[51],"160,000":[53],"transistors,":[54],"ran":[56],"at":[57],"7.25":[58],"MHz.":[59]},"counts_by_year":[{"year":2023,"cited_by_count":1},{"year":2016,"cited_by_count":1},{"year":2014,"cited_by_count":3},{"year":2013,"cited_by_count":1},{"year":2012,"cited_by_count":1}],"updated_date":"2026-06-11T09:08:48.828518","created_date":"2025-10-10T00:00:00"}
