{"id":"https://openalex.org/W2033578273","doi":"https://doi.org/10.1145/1375527.1375539","title":"A freespace crossbar for multi-core processors","display_name":"A freespace crossbar for multi-core processors","publication_year":2008,"publication_date":"2008-06-07","ids":{"openalex":"https://openalex.org/W2033578273","doi":"https://doi.org/10.1145/1375527.1375539","mag":"2033578273"},"language":"en","primary_location":{"id":"doi:10.1145/1375527.1375539","is_oa":false,"landing_page_url":"https://doi.org/10.1145/1375527.1375539","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 22nd annual international conference on Supercomputing","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5020979481","display_name":"Michel N. Victor","orcid":null},"institutions":[],"countries":[],"is_corresponding":true,"raw_author_name":"Michel N. Victor","raw_affiliation_strings":["Exaconnect, Sunnyside, NY, USA"],"affiliations":[{"raw_affiliation_string":"Exaconnect, Sunnyside, NY, USA","institution_ids":[]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5008579506","display_name":"A. Silzars","orcid":null},"institutions":[{"id":"https://openalex.org/I1343973766","display_name":"Acxiom (United States)","ror":"https://ror.org/00pv14226","country_code":"US","type":"company","lineage":["https://openalex.org/I1343973766"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Aris K. Silzars","raw_affiliation_strings":["Exaconnect, Sammamish, WA, USA"],"affiliations":[{"raw_affiliation_string":"Exaconnect, Sammamish, WA, USA","institution_ids":["https://openalex.org/I1343973766"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5025991850","display_name":"Edward S. Davidson","orcid":null},"institutions":[{"id":"https://openalex.org/I27837315","display_name":"University of Michigan\u2013Ann Arbor","ror":"https://ror.org/00jmfr291","country_code":"US","type":"education","lineage":["https://openalex.org/I27837315"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Edward S. Davidson","raw_affiliation_strings":["University of Michigan, Ann Arbor, MI, USA"],"affiliations":[{"raw_affiliation_string":"University of Michigan, Ann Arbor, MI, USA","institution_ids":["https://openalex.org/I27837315"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":3,"corresponding_author_ids":["https://openalex.org/A5020979481"],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":0,"citation_normalized_percentile":{"value":0.1042439,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":null,"issue":null,"first_page":"56","last_page":"62"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.9944999814033508,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.9944999814033508,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9876000285148621,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11601","display_name":"Neuroscience and Neural Engineering","score":0.9786999821662903,"subfield":{"id":"https://openalex.org/subfields/2804","display_name":"Cellular and Molecular Neuroscience"},"field":{"id":"https://openalex.org/fields/28","display_name":"Neuroscience"},"domain":{"id":"https://openalex.org/domains/1","display_name":"Life Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/crossbar-switch","display_name":"Crossbar switch","score":0.9889565706253052},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.6705244183540344},{"id":"https://openalex.org/keywords/interconnection","display_name":"Interconnection","score":0.649491548538208},{"id":"https://openalex.org/keywords/latency","display_name":"Latency (audio)","score":0.612909197807312},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.4653172492980957},{"id":"https://openalex.org/keywords/multi-core-processor","display_name":"Multi-core processor","score":0.4359104633331299},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.39585423469543457},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.3491148352622986},{"id":"https://openalex.org/keywords/computer-network","display_name":"Computer network","score":0.23234161734580994},{"id":"https://openalex.org/keywords/telecommunications","display_name":"Telecommunications","score":0.15197238326072693}],"concepts":[{"id":"https://openalex.org/C29984679","wikidata":"https://www.wikidata.org/wiki/Q1929149","display_name":"Crossbar switch","level":2,"score":0.9889565706253052},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6705244183540344},{"id":"https://openalex.org/C123745756","wikidata":"https://www.wikidata.org/wiki/Q1665949","display_name":"Interconnection","level":2,"score":0.649491548538208},{"id":"https://openalex.org/C82876162","wikidata":"https://www.wikidata.org/wiki/Q17096504","display_name":"Latency (audio)","level":2,"score":0.612909197807312},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.4653172492980957},{"id":"https://openalex.org/C78766204","wikidata":"https://www.wikidata.org/wiki/Q555032","display_name":"Multi-core processor","level":2,"score":0.4359104633331299},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.39585423469543457},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.3491148352622986},{"id":"https://openalex.org/C31258907","wikidata":"https://www.wikidata.org/wiki/Q1301371","display_name":"Computer network","level":1,"score":0.23234161734580994},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.15197238326072693}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1145/1375527.1375539","is_oa":false,"landing_page_url":"https://doi.org/10.1145/1375527.1375539","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 22nd annual international conference on Supercomputing","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":8,"referenced_works":["https://openalex.org/W1826803418","https://openalex.org/W1996270789","https://openalex.org/W2031577623","https://openalex.org/W2077083717","https://openalex.org/W2088499174","https://openalex.org/W2101791918","https://openalex.org/W2143234403","https://openalex.org/W2545500460"],"related_works":["https://openalex.org/W2145932742","https://openalex.org/W1874409533","https://openalex.org/W2554791727","https://openalex.org/W1981395029","https://openalex.org/W2108083791","https://openalex.org/W4250137794","https://openalex.org/W4297664933","https://openalex.org/W2145017421","https://openalex.org/W3023876411","https://openalex.org/W123152114"],"abstract_inverted_index":{"A":[0],"new":[1],"package-level":[2,16],"interconnect":[3],"is":[4],"described":[5],"that":[6,75],"adapts":[7],"carbon":[8],"nanoemissive":[9],"display":[10],"technology":[11],"to":[12],"create":[13],"an":[14],"inexpensive":[15],"freespace":[17],"crossbar":[18,46,49,66],"with":[19],"single-cycle":[20],"source-to-target":[21],"latency.":[22],"Interconnections":[23],"are":[24,37,53],"made":[25],"using":[26],"filamentary":[27],"electron":[28],"beams":[29,36],"as":[30],"the":[31,62,65,77],"data":[32],"transmission":[33],"medium.":[34],"The":[35,48],"electrostatically":[38],"steered,":[39],"enabling":[40],"very":[41],"large,":[42],"low":[43],"latency":[44],"inter-chip":[45],"networks.":[47],"and":[50,67],"associated":[51],"package":[52],"built":[54],"entirely":[55],"from":[56],"existing":[57],"technology.":[58],"This":[59],"paper":[60],"describes":[61],"operation":[63],"of":[64],"presents":[68],"a":[69,73],"conceptual":[70],"design":[71],"for":[72],"processor":[74],"uses":[76],"crossbar.":[78]},"counts_by_year":[],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}