{"id":"https://openalex.org/W2031871682","doi":"https://doi.org/10.1145/1371579.1371582","title":"Parametric Yield Modeling and Simulations of FPGA Circuits Considering Within-Die Delay Variations","display_name":"Parametric Yield Modeling and Simulations of FPGA Circuits Considering Within-Die Delay Variations","publication_year":2008,"publication_date":"2008-06-01","ids":{"openalex":"https://openalex.org/W2031871682","doi":"https://doi.org/10.1145/1371579.1371582","mag":"2031871682"},"language":"en","primary_location":{"id":"doi:10.1145/1371579.1371582","is_oa":false,"landing_page_url":"https://doi.org/10.1145/1371579.1371582","pdf_url":null,"source":{"id":"https://openalex.org/S112809824","display_name":"ACM Transactions on Reconfigurable Technology and Systems","issn_l":"1936-7406","issn":["1936-7406","1936-7414"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319798","host_organization_name":"Association for Computing Machinery","host_organization_lineage":["https://openalex.org/P4310319798"],"host_organization_lineage_names":["Association for Computing Machinery"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"ACM Transactions on Reconfigurable Technology and Systems","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5048050040","display_name":"Pete Sedcole","orcid":null},"institutions":[{"id":"https://openalex.org/I47508984","display_name":"Imperial College London","ror":"https://ror.org/041kmwe10","country_code":"GB","type":"education","lineage":["https://openalex.org/I47508984"]}],"countries":["GB"],"is_corresponding":true,"raw_author_name":"Pete Sedcole","raw_affiliation_strings":["Imperial College London","Imperial College London,#TAB#"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Imperial College London","institution_ids":["https://openalex.org/I47508984"]},{"raw_affiliation_string":"Imperial College London,#TAB#","institution_ids":["https://openalex.org/I47508984"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5091532722","display_name":"Peter Y. K. Cheung","orcid":"https://orcid.org/0000-0002-8236-1816"},"institutions":[{"id":"https://openalex.org/I47508984","display_name":"Imperial College London","ror":"https://ror.org/041kmwe10","country_code":"GB","type":"education","lineage":["https://openalex.org/I47508984"]}],"countries":["GB"],"is_corresponding":false,"raw_author_name":"Peter Y. K. Cheung","raw_affiliation_strings":["Imperial College London","Imperial College London,#TAB#"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Imperial College London","institution_ids":["https://openalex.org/I47508984"]},{"raw_affiliation_string":"Imperial College London,#TAB#","institution_ids":["https://openalex.org/I47508984"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":2,"corresponding_author_ids":["https://openalex.org/A5048050040"],"corresponding_institution_ids":["https://openalex.org/I47508984"],"apc_list":null,"apc_paid":null,"fwci":2.0348,"has_fulltext":false,"cited_by_count":15,"citation_normalized_percentile":{"value":0.8650556,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":90,"max":97},"biblio":{"volume":"1","issue":"2","first_page":"1","last_page":"28"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/reconfigurability","display_name":"Reconfigurability","score":0.83176589012146},{"id":"https://openalex.org/keywords/parametric-statistics","display_name":"Parametric statistics","score":0.7131154537200928},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.6851361393928528},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.6675541400909424},{"id":"https://openalex.org/keywords/control-reconfiguration","display_name":"Control reconfiguration","score":0.6531236171722412},{"id":"https://openalex.org/keywords/static-timing-analysis","display_name":"Static timing analysis","score":0.5309606790542603},{"id":"https://openalex.org/keywords/circuit-design","display_name":"Circuit design","score":0.474031001329422},{"id":"https://openalex.org/keywords/electronic-circuit","display_name":"Electronic circuit","score":0.41506925225257874},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.3699701428413391},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.20093700289726257},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.12721222639083862},{"id":"https://openalex.org/keywords/mathematics","display_name":"Mathematics","score":0.11691060662269592},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.11113026738166809},{"id":"https://openalex.org/keywords/telecommunications","display_name":"Telecommunications","score":0.08196339011192322}],"concepts":[{"id":"https://openalex.org/C2780149590","wikidata":"https://www.wikidata.org/wiki/Q7302742","display_name":"Reconfigurability","level":2,"score":0.83176589012146},{"id":"https://openalex.org/C117251300","wikidata":"https://www.wikidata.org/wiki/Q1849855","display_name":"Parametric statistics","level":2,"score":0.7131154537200928},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6851361393928528},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.6675541400909424},{"id":"https://openalex.org/C119701452","wikidata":"https://www.wikidata.org/wiki/Q5165881","display_name":"Control reconfiguration","level":2,"score":0.6531236171722412},{"id":"https://openalex.org/C93682380","wikidata":"https://www.wikidata.org/wiki/Q2025226","display_name":"Static timing analysis","level":2,"score":0.5309606790542603},{"id":"https://openalex.org/C190560348","wikidata":"https://www.wikidata.org/wiki/Q3245116","display_name":"Circuit design","level":2,"score":0.474031001329422},{"id":"https://openalex.org/C134146338","wikidata":"https://www.wikidata.org/wiki/Q1815901","display_name":"Electronic circuit","level":2,"score":0.41506925225257874},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.3699701428413391},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.20093700289726257},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.12721222639083862},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.11691060662269592},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.11113026738166809},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.08196339011192322},{"id":"https://openalex.org/C105795698","wikidata":"https://www.wikidata.org/wiki/Q12483","display_name":"Statistics","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1145/1371579.1371582","is_oa":false,"landing_page_url":"https://doi.org/10.1145/1371579.1371582","pdf_url":null,"source":{"id":"https://openalex.org/S112809824","display_name":"ACM Transactions on Reconfigurable Technology and Systems","issn_l":"1936-7406","issn":["1936-7406","1936-7414"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319798","host_organization_name":"Association for Computing Machinery","host_organization_lineage":["https://openalex.org/P4310319798"],"host_organization_lineage_names":["Association for Computing Machinery"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"ACM Transactions on Reconfigurable Technology and Systems","raw_type":"journal-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[{"id":"https://openalex.org/G8360944955","display_name":null,"funder_award_id":"EP/C549481/1","funder_id":"https://openalex.org/F4320334627","funder_display_name":"Engineering and Physical Sciences Research Council"}],"funders":[{"id":"https://openalex.org/F4320334627","display_name":"Engineering and Physical Sciences Research Council","ror":"https://ror.org/0439y7842"}],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":29,"referenced_works":["https://openalex.org/W1525409241","https://openalex.org/W1526642634","https://openalex.org/W1532888190","https://openalex.org/W1971584660","https://openalex.org/W1984105700","https://openalex.org/W1987383141","https://openalex.org/W1991353737","https://openalex.org/W2084083833","https://openalex.org/W2096227207","https://openalex.org/W2114131053","https://openalex.org/W2115596773","https://openalex.org/W2123355738","https://openalex.org/W2129883611","https://openalex.org/W2133097426","https://openalex.org/W2139637699","https://openalex.org/W2141682861","https://openalex.org/W2143901474","https://openalex.org/W2150107614","https://openalex.org/W2154665706","https://openalex.org/W2154776455","https://openalex.org/W2155042027","https://openalex.org/W2161344439","https://openalex.org/W2163262735","https://openalex.org/W2165740397","https://openalex.org/W2532498749","https://openalex.org/W2913252637","https://openalex.org/W4234168281","https://openalex.org/W4299617642","https://openalex.org/W6631407737"],"related_works":["https://openalex.org/W2152623100","https://openalex.org/W2096417281","https://openalex.org/W25204318","https://openalex.org/W2077035242","https://openalex.org/W2138895528","https://openalex.org/W3042643149","https://openalex.org/W2056979595","https://openalex.org/W1999203047","https://openalex.org/W3201977823","https://openalex.org/W2362203107"],"abstract_inverted_index":{"Variations":[0],"in":[1,7,9,111],"the":[2,14,55,67,71],"semiconductor":[3],"fabrication":[4],"process":[5],"results":[6],"differences":[8],"parameters":[10],"between":[11],"transistors":[12],"on":[13,70],"same":[15],"die,":[16],"a":[17],"problem":[18],"exacerbated":[19],"by":[20,35,51,98,127],"lithographic":[21],"scaling.":[22],"Field-Programmable":[23],"Gate":[24],"Arrays":[25],"may":[26],"be":[27,125],"able":[28],"to":[29,81,100],"compensate":[30],"for":[31,45,66,76,83],"within-die":[32,47],"delay":[33,49],"variability,":[34],"judicious":[36],"use":[37],"of":[38],"reconfigurability.":[39],"This":[40],"article":[41],"presents":[42],"two":[43],"strategies":[44,78],"compensating":[46],"stochastic":[48],"variability":[50],"using":[52,118],"reconfiguration:":[53],"reconfiguring":[54],"entire":[56],"FPGA,":[57],"and":[58,79,114,121],"relocating":[59],"subcircuits":[60],"within":[61],"an":[62],"FPGA.":[63],"Analytical":[64],"models":[65,82,95],"theoretical":[68],"bounds":[69],"achievable":[72],"gains":[73],"are":[74,96,116],"derived":[75],"both":[77],"compared":[80],"worst-case":[84],"design":[85],"as":[86,88],"well":[87],"statistical":[89],"static":[90],"timing":[91,115],"analysis":[92],"(SSTA).":[93],"All":[94],"validated":[97],"comparison":[99],"circuit-level":[101],"Monte":[102],"Carlo":[103],"simulations.":[104],"It":[105],"is":[106],"demonstrated":[107],"that":[108],"significant":[109],"improvements":[110,123],"circuit":[112],"yield":[113],"possible":[117],"SSTA":[119],"alone,":[120],"these":[122],"can":[124],"enhanced":[126],"employing":[128],"reconfiguration-based":[129],"techniques.":[130]},"counts_by_year":[{"year":2017,"cited_by_count":2},{"year":2016,"cited_by_count":1},{"year":2015,"cited_by_count":1},{"year":2014,"cited_by_count":3},{"year":2013,"cited_by_count":2}],"updated_date":"2026-05-21T06:26:12.895304","created_date":"2025-10-10T00:00:00"}
