{"id":"https://openalex.org/W2034549010","doi":"https://doi.org/10.1145/1367045.1367062","title":"Power-aware SoC test planning for effective utilization of port-scalable testers","display_name":"Power-aware SoC test planning for effective utilization of port-scalable testers","publication_year":2008,"publication_date":"2008-07-01","ids":{"openalex":"https://openalex.org/W2034549010","doi":"https://doi.org/10.1145/1367045.1367062","mag":"2034549010"},"language":"en","primary_location":{"id":"doi:10.1145/1367045.1367062","is_oa":false,"landing_page_url":"https://doi.org/10.1145/1367045.1367062","pdf_url":null,"source":{"id":"https://openalex.org/S105046310","display_name":"ACM Transactions on Design Automation of Electronic Systems","issn_l":"1084-4309","issn":["1084-4309","1557-7309"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319798","host_organization_name":"Association for Computing Machinery","host_organization_lineage":["https://openalex.org/P4310319798"],"host_organization_lineage_names":["Association for Computing Machinery"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"ACM Transactions on Design Automation of Electronic Systems","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5069836668","display_name":"Anuja Sehgal","orcid":null},"institutions":[{"id":"https://openalex.org/I170897317","display_name":"Duke University","ror":"https://ror.org/00py81415","country_code":"US","type":"education","lineage":["https://openalex.org/I170897317"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Anuja Sehgal","raw_affiliation_strings":["Duke University, Durham, NC"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Duke University, Durham, NC","institution_ids":["https://openalex.org/I170897317"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5083568419","display_name":"Sudarshan Bahukudumbi","orcid":null},"institutions":[{"id":"https://openalex.org/I170897317","display_name":"Duke University","ror":"https://ror.org/00py81415","country_code":"US","type":"education","lineage":["https://openalex.org/I170897317"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Sudarshan Bahukudumbi","raw_affiliation_strings":["Duke University, Durham, NC"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Duke University, Durham, NC","institution_ids":["https://openalex.org/I170897317"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5033880864","display_name":"Krishnendu Chakrabarty","orcid":"https://orcid.org/0000-0003-4475-6435"},"institutions":[{"id":"https://openalex.org/I170897317","display_name":"Duke University","ror":"https://ror.org/00py81415","country_code":"US","type":"education","lineage":["https://openalex.org/I170897317"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Krishnendu Chakrabarty","raw_affiliation_strings":["Duke University, Durham, NC"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Duke University, Durham, NC","institution_ids":["https://openalex.org/I170897317"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":3,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":0.6906,"has_fulltext":false,"cited_by_count":7,"citation_normalized_percentile":{"value":0.75115207,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":90,"max":96},"biblio":{"volume":"13","issue":"3","first_page":"1","last_page":"19"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T14117","display_name":"Integrated Circuits and Semiconductor Failure Analysis","score":0.9991000294685364,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9976999759674072,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.8458353281021118},{"id":"https://openalex.org/keywords/scalability","display_name":"Scalability","score":0.7639154195785522},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.5805341005325317},{"id":"https://openalex.org/keywords/system-on-a-chip","display_name":"System on a chip","score":0.5752214789390564},{"id":"https://openalex.org/keywords/test-compression","display_name":"Test compression","score":0.5314515829086304},{"id":"https://openalex.org/keywords/scheduling","display_name":"Scheduling (production processes)","score":0.45636409521102905},{"id":"https://openalex.org/keywords/port","display_name":"Port (circuit theory)","score":0.45357808470726013},{"id":"https://openalex.org/keywords/test-strategy","display_name":"Test strategy","score":0.45306074619293213},{"id":"https://openalex.org/keywords/power","display_name":"Power (physics)","score":0.43478959798812866},{"id":"https://openalex.org/keywords/automatic-test-pattern-generation","display_name":"Automatic test pattern generation","score":0.3723523020744324},{"id":"https://openalex.org/keywords/real-time-computing","display_name":"Real-time computing","score":0.3644148111343384},{"id":"https://openalex.org/keywords/electronic-circuit","display_name":"Electronic circuit","score":0.21781614422798157},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.09659290313720703}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.8458353281021118},{"id":"https://openalex.org/C48044578","wikidata":"https://www.wikidata.org/wiki/Q727490","display_name":"Scalability","level":2,"score":0.7639154195785522},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.5805341005325317},{"id":"https://openalex.org/C118021083","wikidata":"https://www.wikidata.org/wiki/Q610398","display_name":"System on a chip","level":2,"score":0.5752214789390564},{"id":"https://openalex.org/C29652920","wikidata":"https://www.wikidata.org/wiki/Q7705757","display_name":"Test compression","level":4,"score":0.5314515829086304},{"id":"https://openalex.org/C206729178","wikidata":"https://www.wikidata.org/wiki/Q2271896","display_name":"Scheduling (production processes)","level":2,"score":0.45636409521102905},{"id":"https://openalex.org/C32802771","wikidata":"https://www.wikidata.org/wiki/Q2443617","display_name":"Port (circuit theory)","level":2,"score":0.45357808470726013},{"id":"https://openalex.org/C188598960","wikidata":"https://www.wikidata.org/wiki/Q7705805","display_name":"Test strategy","level":3,"score":0.45306074619293213},{"id":"https://openalex.org/C163258240","wikidata":"https://www.wikidata.org/wiki/Q25342","display_name":"Power (physics)","level":2,"score":0.43478959798812866},{"id":"https://openalex.org/C17626397","wikidata":"https://www.wikidata.org/wiki/Q837455","display_name":"Automatic test pattern generation","level":3,"score":0.3723523020744324},{"id":"https://openalex.org/C79403827","wikidata":"https://www.wikidata.org/wiki/Q3988","display_name":"Real-time computing","level":1,"score":0.3644148111343384},{"id":"https://openalex.org/C134146338","wikidata":"https://www.wikidata.org/wiki/Q1815901","display_name":"Electronic circuit","level":2,"score":0.21781614422798157},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.09659290313720703},{"id":"https://openalex.org/C77088390","wikidata":"https://www.wikidata.org/wiki/Q8513","display_name":"Database","level":1,"score":0.0},{"id":"https://openalex.org/C121332964","wikidata":"https://www.wikidata.org/wiki/Q413","display_name":"Physics","level":0,"score":0.0},{"id":"https://openalex.org/C62520636","wikidata":"https://www.wikidata.org/wiki/Q944","display_name":"Quantum mechanics","level":1,"score":0.0},{"id":"https://openalex.org/C2777904410","wikidata":"https://www.wikidata.org/wiki/Q7397","display_name":"Software","level":2,"score":0.0},{"id":"https://openalex.org/C162324750","wikidata":"https://www.wikidata.org/wiki/Q8134","display_name":"Economics","level":0,"score":0.0},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.0},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.0},{"id":"https://openalex.org/C21547014","wikidata":"https://www.wikidata.org/wiki/Q1423657","display_name":"Operations management","level":1,"score":0.0},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.0}],"mesh":[],"locations_count":2,"locations":[{"id":"doi:10.1145/1367045.1367062","is_oa":false,"landing_page_url":"https://doi.org/10.1145/1367045.1367062","pdf_url":null,"source":{"id":"https://openalex.org/S105046310","display_name":"ACM Transactions on Design Automation of Electronic Systems","issn_l":"1084-4309","issn":["1084-4309","1557-7309"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319798","host_organization_name":"Association for Computing Machinery","host_organization_lineage":["https://openalex.org/P4310319798"],"host_organization_lineage_names":["Association for Computing Machinery"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"ACM Transactions on Design Automation of Electronic Systems","raw_type":"journal-article"},{"id":"pmh:oai:CiteSeerX.psu:10.1.1.161.1147","is_oa":false,"landing_page_url":"http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.161.1147","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"http://www.ee.duke.edu/~krish/a53-sehgal.pdf","raw_type":"text"}],"best_oa_location":null,"sustainable_development_goals":[{"display_name":"Affordable and clean energy","id":"https://metadata.un.org/sdg/7","score":0.7099999785423279}],"awards":[{"id":"https://openalex.org/G2999483624","display_name":null,"funder_award_id":"CCR-0204077","funder_id":"https://openalex.org/F4320306076","funder_display_name":"National Science Foundation"}],"funders":[{"id":"https://openalex.org/F4320306076","display_name":"National Science Foundation","ror":"https://ror.org/021nxhr62"}],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":34,"referenced_works":["https://openalex.org/W1552973677","https://openalex.org/W1596724070","https://openalex.org/W1832971077","https://openalex.org/W1884658820","https://openalex.org/W1965261507","https://openalex.org/W2075105459","https://openalex.org/W2086405605","https://openalex.org/W2100927656","https://openalex.org/W2103799547","https://openalex.org/W2104343580","https://openalex.org/W2104548962","https://openalex.org/W2109023668","https://openalex.org/W2112420302","https://openalex.org/W2113475058","https://openalex.org/W2114165504","https://openalex.org/W2114768214","https://openalex.org/W2118204515","https://openalex.org/W2120246395","https://openalex.org/W2124658657","https://openalex.org/W2125474840","https://openalex.org/W2133918004","https://openalex.org/W2138784704","https://openalex.org/W2140035276","https://openalex.org/W2140479749","https://openalex.org/W2145458704","https://openalex.org/W2151243068","https://openalex.org/W2151760281","https://openalex.org/W2159249733","https://openalex.org/W2165642910","https://openalex.org/W2169449309","https://openalex.org/W2170504575","https://openalex.org/W2170533364","https://openalex.org/W3149147135","https://openalex.org/W4248309809"],"related_works":["https://openalex.org/W1978748630","https://openalex.org/W2463298697","https://openalex.org/W2166065438","https://openalex.org/W2156203118","https://openalex.org/W607208775","https://openalex.org/W2090728180","https://openalex.org/W2140149668","https://openalex.org/W2127356388","https://openalex.org/W3035027313","https://openalex.org/W2034549010"],"abstract_inverted_index":{"Many":[0],"system-on-chip":[1],"(SoC)":[2],"integrated":[3],"circuits":[4],"contain":[5],"embedded":[6,121],"cores":[7],"with":[8],"different":[9,38],"scan":[10,49,116],"frequencies.":[11],"To":[12],"better":[13],"meet":[14],"the":[15,42,60,67,73,99,152],"test":[16,61,69,83,95,128,139,148,159],"requirements":[17],"for":[18,48,63,119,146],"such":[19],"heterogeneous":[20],"SoCs,":[21],"leading":[22],"tester":[23,45],"companies":[24],"have":[25],"recently":[26],"introduced":[27],"port-scalable":[28,134],"testers,":[29],"which":[30],"can":[31,58],"simultaneously":[32],"drive":[33],"groups":[34],"of":[35,44,90,138,154],"channels":[36,46],"at":[37],"data":[39,117],"rates.":[40],"However,":[41],"number":[43],"available":[47],"testing":[50],"is":[51],"limited;":[52],"therefore,":[53],"a":[54,64,81,114,126],"higher":[55],"shift":[56],"frequency":[57],"increase":[59],"time":[62],"core":[65],"if":[66],"resulting":[68],"access":[70,77],"architecture":[71],"reduces":[72],"bit-width":[74],"used":[75],"to":[76,92,104,131,150],"it.":[78],"We":[79,97,123],"present":[80],"scalable":[82],"planning":[84,129],"technique":[85,130],"that":[86,112],"exploits":[87],"port":[88],"scalability":[89],"testers":[91,135],"reduce":[93],"SoC":[94],"time.":[96,160],"compare":[98],"proposed":[100],"heuristic":[101],"optimization":[102],"method":[103],"two":[105],"baseline":[106],"methods":[107],"based":[108],"on":[109,157],"prior":[110],"works":[111],"use":[113],"single":[115],"rate":[118],"all":[120],"cores.":[122],"also":[124],"propose":[125],"power-aware":[127,147],"effectively":[132],"utilize":[133],"under":[136],"constraints":[137,156],"power":[140,155],"consumption.":[141],"Experimental":[142],"results":[143],"are":[144],"presented":[145],"scheduling":[149],"illustrate":[151],"impact":[153],"overall":[158]},"counts_by_year":[{"year":2017,"cited_by_count":1},{"year":2014,"cited_by_count":2},{"year":2013,"cited_by_count":1},{"year":2012,"cited_by_count":1}],"updated_date":"2026-06-11T09:08:48.828518","created_date":"2025-10-10T00:00:00"}