{"id":"https://openalex.org/W2117591452","doi":"https://doi.org/10.1145/1366110.1366195","title":"Efficient and optimal post-layout double-cut via insertion by network relaxation and min-cost maximum flow","display_name":"Efficient and optimal post-layout double-cut via insertion by network relaxation and min-cost maximum flow","publication_year":2008,"publication_date":"2008-05-04","ids":{"openalex":"https://openalex.org/W2117591452","doi":"https://doi.org/10.1145/1366110.1366195","mag":"2117591452"},"language":"en","primary_location":{"id":"doi:10.1145/1366110.1366195","is_oa":false,"landing_page_url":"https://doi.org/10.1145/1366110.1366195","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 18th ACM Great Lakes symposium on VLSI","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5042481061","display_name":"Lun-Chun Wei","orcid":null},"institutions":[{"id":"https://openalex.org/I148366613","display_name":"National Yang Ming Chiao Tung University","ror":"https://ror.org/00se2k293","country_code":"TW","type":"education","lineage":["https://openalex.org/I148366613"]}],"countries":["TW"],"is_corresponding":true,"raw_author_name":"Lun-Chun Wei","raw_affiliation_strings":["National Chiao Tung University, Hsinchu, Taiwan Roc","National Chiao Tung University , Hsinchu, Taiwan, ROC"],"affiliations":[{"raw_affiliation_string":"National Chiao Tung University, Hsinchu, Taiwan Roc","institution_ids":["https://openalex.org/I148366613"]},{"raw_affiliation_string":"National Chiao Tung University , Hsinchu, Taiwan, ROC","institution_ids":["https://openalex.org/I148366613"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5021615416","display_name":"Hung-Ming Chen","orcid":"https://orcid.org/0000-0001-8173-3131"},"institutions":[{"id":"https://openalex.org/I148366613","display_name":"National Yang Ming Chiao Tung University","ror":"https://ror.org/00se2k293","country_code":"TW","type":"education","lineage":["https://openalex.org/I148366613"]}],"countries":["TW"],"is_corresponding":false,"raw_author_name":"Hung-Ming Chen","raw_affiliation_strings":["National Chiao Tung University, Hsinchu, Taiwan Roc","National Chiao Tung University , Hsinchu, Taiwan, ROC"],"affiliations":[{"raw_affiliation_string":"National Chiao Tung University, Hsinchu, Taiwan Roc","institution_ids":["https://openalex.org/I148366613"]},{"raw_affiliation_string":"National Chiao Tung University , Hsinchu, Taiwan, ROC","institution_ids":["https://openalex.org/I148366613"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5069617930","display_name":"Lida Huang","orcid":"https://orcid.org/0000-0002-2663-6221"},"institutions":[{"id":"https://openalex.org/I4210126997","display_name":"Software and Engineering Associates (United States)","ror":"https://ror.org/03qt0ma29","country_code":"US","type":"company","lineage":["https://openalex.org/I4210126997"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Li-Da Huang","raw_affiliation_strings":["Magma Design Automation Inc., Austin, TX, USA","[Magma Design-Automation, Inc., Austin, TX, USA]"],"affiliations":[{"raw_affiliation_string":"Magma Design Automation Inc., Austin, TX, USA","institution_ids":[]},{"raw_affiliation_string":"[Magma Design-Automation, Inc., Austin, TX, USA]","institution_ids":["https://openalex.org/I4210126997"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5049009075","display_name":"Sarah Songjie Xu","orcid":null},"institutions":[{"id":"https://openalex.org/I4210126997","display_name":"Software and Engineering Associates (United States)","ror":"https://ror.org/03qt0ma29","country_code":"US","type":"company","lineage":["https://openalex.org/I4210126997"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Sarah Songjie Xu","raw_affiliation_strings":["Magma Design Automation Inc., Austin, TX, USA","[Magma Design-Automation, Inc., Austin, TX, USA]"],"affiliations":[{"raw_affiliation_string":"Magma Design Automation Inc., Austin, TX, USA","institution_ids":[]},{"raw_affiliation_string":"[Magma Design-Automation, Inc., Austin, TX, USA]","institution_ids":["https://openalex.org/I4210126997"]}]}],"institutions":[],"countries_distinct_count":2,"institutions_distinct_count":4,"corresponding_author_ids":["https://openalex.org/A5042481061"],"corresponding_institution_ids":["https://openalex.org/I148366613"],"apc_list":null,"apc_paid":null,"fwci":0.3329,"has_fulltext":false,"cited_by_count":1,"citation_normalized_percentile":{"value":0.65172248,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":null,"issue":null,"first_page":"359","last_page":"362"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/very-large-scale-integration","display_name":"Very-large-scale integration","score":0.6798735857009888},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.627398669719696},{"id":"https://openalex.org/keywords/maximum-flow-problem","display_name":"Maximum flow problem","score":0.5946933031082153},{"id":"https://openalex.org/keywords/yield","display_name":"Yield (engineering)","score":0.5610044002532959},{"id":"https://openalex.org/keywords/flow","display_name":"Flow (mathematics)","score":0.5553921461105347},{"id":"https://openalex.org/keywords/flow-network","display_name":"Flow network","score":0.5238999128341675},{"id":"https://openalex.org/keywords/design-flow","display_name":"Design flow","score":0.44669198989868164},{"id":"https://openalex.org/keywords/mathematical-optimization","display_name":"Mathematical optimization","score":0.441297709941864},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.42095521092414856},{"id":"https://openalex.org/keywords/integrated-circuit-layout","display_name":"Integrated circuit layout","score":0.41466018557548523},{"id":"https://openalex.org/keywords/reliability-engineering","display_name":"Reliability engineering","score":0.38413190841674805},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.3387411832809448},{"id":"https://openalex.org/keywords/topology","display_name":"Topology (electrical circuits)","score":0.33647245168685913},{"id":"https://openalex.org/keywords/integrated-circuit","display_name":"Integrated circuit","score":0.2792338728904724},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.2259754240512848},{"id":"https://openalex.org/keywords/mathematics","display_name":"Mathematics","score":0.2067348062992096},{"id":"https://openalex.org/keywords/materials-science","display_name":"Materials science","score":0.15437012910842896},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.15390625596046448},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.08191612362861633}],"concepts":[{"id":"https://openalex.org/C14580979","wikidata":"https://www.wikidata.org/wiki/Q876049","display_name":"Very-large-scale integration","level":2,"score":0.6798735857009888},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.627398669719696},{"id":"https://openalex.org/C157469704","wikidata":"https://www.wikidata.org/wiki/Q2585642","display_name":"Maximum flow problem","level":2,"score":0.5946933031082153},{"id":"https://openalex.org/C134121241","wikidata":"https://www.wikidata.org/wiki/Q899301","display_name":"Yield (engineering)","level":2,"score":0.5610044002532959},{"id":"https://openalex.org/C38349280","wikidata":"https://www.wikidata.org/wiki/Q1434290","display_name":"Flow (mathematics)","level":2,"score":0.5553921461105347},{"id":"https://openalex.org/C114809511","wikidata":"https://www.wikidata.org/wiki/Q1412924","display_name":"Flow network","level":2,"score":0.5238999128341675},{"id":"https://openalex.org/C37135326","wikidata":"https://www.wikidata.org/wiki/Q931942","display_name":"Design flow","level":2,"score":0.44669198989868164},{"id":"https://openalex.org/C126255220","wikidata":"https://www.wikidata.org/wiki/Q141495","display_name":"Mathematical optimization","level":1,"score":0.441297709941864},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.42095521092414856},{"id":"https://openalex.org/C2765594","wikidata":"https://www.wikidata.org/wiki/Q2624187","display_name":"Integrated circuit layout","level":3,"score":0.41466018557548523},{"id":"https://openalex.org/C200601418","wikidata":"https://www.wikidata.org/wiki/Q2193887","display_name":"Reliability engineering","level":1,"score":0.38413190841674805},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.3387411832809448},{"id":"https://openalex.org/C184720557","wikidata":"https://www.wikidata.org/wiki/Q7825049","display_name":"Topology (electrical circuits)","level":2,"score":0.33647245168685913},{"id":"https://openalex.org/C530198007","wikidata":"https://www.wikidata.org/wiki/Q80831","display_name":"Integrated circuit","level":2,"score":0.2792338728904724},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.2259754240512848},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.2067348062992096},{"id":"https://openalex.org/C192562407","wikidata":"https://www.wikidata.org/wiki/Q228736","display_name":"Materials science","level":0,"score":0.15437012910842896},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.15390625596046448},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.08191612362861633},{"id":"https://openalex.org/C191897082","wikidata":"https://www.wikidata.org/wiki/Q11467","display_name":"Metallurgy","level":1,"score":0.0},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.0},{"id":"https://openalex.org/C2524010","wikidata":"https://www.wikidata.org/wiki/Q8087","display_name":"Geometry","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1145/1366110.1366195","is_oa":false,"landing_page_url":"https://doi.org/10.1145/1366110.1366195","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 18th ACM Great Lakes symposium on VLSI","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":13,"referenced_works":["https://openalex.org/W2061083860","https://openalex.org/W2075614116","https://openalex.org/W2092362792","https://openalex.org/W2106430949","https://openalex.org/W2107575459","https://openalex.org/W2113734214","https://openalex.org/W2115004507","https://openalex.org/W2145287211","https://openalex.org/W2148390345","https://openalex.org/W2148651340","https://openalex.org/W2149121027","https://openalex.org/W2158315456","https://openalex.org/W2168979836"],"related_works":["https://openalex.org/W2375873432","https://openalex.org/W4206915070","https://openalex.org/W2531764854","https://openalex.org/W2098682899","https://openalex.org/W3161514703","https://openalex.org/W2141299097","https://openalex.org/W1851375266","https://openalex.org/W2610002854","https://openalex.org/W3141113327","https://openalex.org/W4206407367"],"abstract_inverted_index":{"As":[0],"VLSI":[1],"design":[2],"complexity":[3],"is":[4,26,85],"continuously":[5],"increasing,":[6],"the":[7,53,74,95],"yield":[8,35],"loss":[9,36],"due":[10,37,93],"to":[11,22,33,38,94],"via":[12,20,25,39,55,69],"failure":[13],"becomes":[14],"more":[15],"significant.":[16],"Adding":[17],"a":[18,27,46],"redundant":[19,54,68],"adjacent":[21],"each":[23],"single":[24],"well-known":[28],"and":[29,61,87],"highly":[30],"recommended":[31],"method":[32],"reduce":[34],"failure.":[40],"In":[41],"this":[42],"paper,":[43],"we":[44,64],"develop":[45],"network-flow-based":[47],"algorithm":[48],"in":[49,72,89],"post-layout":[50],"stage":[51],"for":[52],"insertion":[56,70],"problem.":[57],"With":[58],"our":[59,83],"novel":[60],"efficient":[62],"approach,":[63],"can":[65],"obtain":[66],"optimal":[67],"solution":[71,92],"improving":[73],"manufacturing":[75],"yield,":[76],"with":[77],"minimal":[78],"fixup":[79],"if":[80],"necessary.":[81],"Moreover,":[82],"approach":[84],"parallel-processing-friendly":[86],"effective":[88],"ECO":[90],"incremental":[91],"nature":[96],"of":[97],"network-flow":[98],"models.":[99]},"counts_by_year":[],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}
