{"id":"https://openalex.org/W1967049292","doi":"https://doi.org/10.1145/1366110.1366186","title":"Efficient tree topology for FPGA interconnect network","display_name":"Efficient tree topology for FPGA interconnect network","publication_year":2008,"publication_date":"2008-05-04","ids":{"openalex":"https://openalex.org/W1967049292","doi":"https://doi.org/10.1145/1366110.1366186","mag":"1967049292"},"language":"en","primary_location":{"id":"doi:10.1145/1366110.1366186","is_oa":false,"landing_page_url":"https://doi.org/10.1145/1366110.1366186","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 18th ACM Great Lakes symposium on VLSI","raw_type":"proceedings-article"},"type":"preprint","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5111822030","display_name":"Zied Marrakchi","orcid":null},"institutions":[{"id":"https://openalex.org/I39804081","display_name":"Sorbonne Universit\u00e9","ror":"https://ror.org/02en5vm52","country_code":"FR","type":"education","lineage":["https://openalex.org/I39804081"]},{"id":"https://openalex.org/I4210129850","display_name":"D\u00e9l\u00e9gation Paris 6","ror":"https://ror.org/03rt48n94","country_code":"FR","type":"government","lineage":["https://openalex.org/I154526488","https://openalex.org/I4210129850"]}],"countries":["FR"],"is_corresponding":false,"raw_author_name":"Marrakchi Zied","raw_affiliation_strings":["Paris 6 university, Paris, France"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Paris 6 university, Paris, France","institution_ids":["https://openalex.org/I4210129850","https://openalex.org/I39804081"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5109922649","display_name":"Mrabet Hayder","orcid":null},"institutions":[{"id":"https://openalex.org/I39804081","display_name":"Sorbonne Universit\u00e9","ror":"https://ror.org/02en5vm52","country_code":"FR","type":"education","lineage":["https://openalex.org/I39804081"]},{"id":"https://openalex.org/I4210129850","display_name":"D\u00e9l\u00e9gation Paris 6","ror":"https://ror.org/03rt48n94","country_code":"FR","type":"government","lineage":["https://openalex.org/I154526488","https://openalex.org/I4210129850"]}],"countries":["FR"],"is_corresponding":false,"raw_author_name":"Mrabet Hayder","raw_affiliation_strings":["Paris 6 university, Paris, France"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Paris 6 university, Paris, France","institution_ids":["https://openalex.org/I4210129850","https://openalex.org/I39804081"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5040282351","display_name":"Emna Amouri","orcid":"https://orcid.org/0000-0003-2107-3658"},"institutions":[{"id":"https://openalex.org/I39804081","display_name":"Sorbonne Universit\u00e9","ror":"https://ror.org/02en5vm52","country_code":"FR","type":"education","lineage":["https://openalex.org/I39804081"]},{"id":"https://openalex.org/I4210129850","display_name":"D\u00e9l\u00e9gation Paris 6","ror":"https://ror.org/03rt48n94","country_code":"FR","type":"government","lineage":["https://openalex.org/I154526488","https://openalex.org/I4210129850"]}],"countries":["FR"],"is_corresponding":false,"raw_author_name":"Amouri Emna","raw_affiliation_strings":["Paris 6 university, Paris, France"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Paris 6 university, Paris, France","institution_ids":["https://openalex.org/I4210129850","https://openalex.org/I39804081"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5103387882","display_name":"Mehrez Habib","orcid":null},"institutions":[{"id":"https://openalex.org/I39804081","display_name":"Sorbonne Universit\u00e9","ror":"https://ror.org/02en5vm52","country_code":"FR","type":"education","lineage":["https://openalex.org/I39804081"]},{"id":"https://openalex.org/I4210129850","display_name":"D\u00e9l\u00e9gation Paris 6","ror":"https://ror.org/03rt48n94","country_code":"FR","type":"government","lineage":["https://openalex.org/I154526488","https://openalex.org/I4210129850"]}],"countries":["FR"],"is_corresponding":false,"raw_author_name":"Mehrez Habib","raw_affiliation_strings":["Paris 6 university, Paris, France"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Paris 6 university, Paris, France","institution_ids":["https://openalex.org/I4210129850","https://openalex.org/I39804081"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":4,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":3.7309,"has_fulltext":false,"cited_by_count":18,"citation_normalized_percentile":{"value":0.92624885,"is_in_top_1_percent":false,"is_in_top_10_percent":true},"cited_by_percentile_year":{"min":90,"max":98},"biblio":{"volume":null,"issue":null,"first_page":"321","last_page":"326"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9994000196456909,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.9993000030517578,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/benchmark","display_name":"Benchmark (surveying)","score":0.7504799365997314},{"id":"https://openalex.org/keywords/network-topology","display_name":"Network topology","score":0.7149779796600342},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.6836374998092651},{"id":"https://openalex.org/keywords/tree","display_name":"Tree (set theory)","score":0.6586722135543823},{"id":"https://openalex.org/keywords/tree-network","display_name":"Tree network","score":0.6039069890975952},{"id":"https://openalex.org/keywords/architecture","display_name":"Architecture","score":0.5870177149772644},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.5459164977073669},{"id":"https://openalex.org/keywords/network-architecture","display_name":"Network architecture","score":0.5416051149368286},{"id":"https://openalex.org/keywords/interconnection","display_name":"Interconnection","score":0.5229297876358032},{"id":"https://openalex.org/keywords/topology","display_name":"Topology (electrical circuits)","score":0.4853488504886627},{"id":"https://openalex.org/keywords/electronic-circuit","display_name":"Electronic circuit","score":0.47881728410720825},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.4769227206707001},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.37659671902656555},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.3435685932636261},{"id":"https://openalex.org/keywords/computer-network","display_name":"Computer network","score":0.2757364809513092},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.19747650623321533},{"id":"https://openalex.org/keywords/mathematics","display_name":"Mathematics","score":0.12629440426826477},{"id":"https://openalex.org/keywords/time-complexity","display_name":"Time complexity","score":0.10611903667449951},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.1059408187866211},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.0781223475933075}],"concepts":[{"id":"https://openalex.org/C185798385","wikidata":"https://www.wikidata.org/wiki/Q1161707","display_name":"Benchmark (surveying)","level":2,"score":0.7504799365997314},{"id":"https://openalex.org/C199845137","wikidata":"https://www.wikidata.org/wiki/Q145490","display_name":"Network topology","level":2,"score":0.7149779796600342},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6836374998092651},{"id":"https://openalex.org/C113174947","wikidata":"https://www.wikidata.org/wiki/Q2859736","display_name":"Tree (set theory)","level":2,"score":0.6586722135543823},{"id":"https://openalex.org/C2781010653","wikidata":"https://www.wikidata.org/wiki/Q12056602","display_name":"Tree network","level":3,"score":0.6039069890975952},{"id":"https://openalex.org/C123657996","wikidata":"https://www.wikidata.org/wiki/Q12271","display_name":"Architecture","level":2,"score":0.5870177149772644},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.5459164977073669},{"id":"https://openalex.org/C193415008","wikidata":"https://www.wikidata.org/wiki/Q639681","display_name":"Network architecture","level":2,"score":0.5416051149368286},{"id":"https://openalex.org/C123745756","wikidata":"https://www.wikidata.org/wiki/Q1665949","display_name":"Interconnection","level":2,"score":0.5229297876358032},{"id":"https://openalex.org/C184720557","wikidata":"https://www.wikidata.org/wiki/Q7825049","display_name":"Topology (electrical circuits)","level":2,"score":0.4853488504886627},{"id":"https://openalex.org/C134146338","wikidata":"https://www.wikidata.org/wiki/Q1815901","display_name":"Electronic circuit","level":2,"score":0.47881728410720825},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.4769227206707001},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.37659671902656555},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.3435685932636261},{"id":"https://openalex.org/C31258907","wikidata":"https://www.wikidata.org/wiki/Q1301371","display_name":"Computer network","level":1,"score":0.2757364809513092},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.19747650623321533},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.12629440426826477},{"id":"https://openalex.org/C311688","wikidata":"https://www.wikidata.org/wiki/Q2393193","display_name":"Time complexity","level":2,"score":0.10611903667449951},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.1059408187866211},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.0781223475933075},{"id":"https://openalex.org/C13280743","wikidata":"https://www.wikidata.org/wiki/Q131089","display_name":"Geodesy","level":1,"score":0.0},{"id":"https://openalex.org/C142362112","wikidata":"https://www.wikidata.org/wiki/Q735","display_name":"Art","level":0,"score":0.0},{"id":"https://openalex.org/C153349607","wikidata":"https://www.wikidata.org/wiki/Q36649","display_name":"Visual arts","level":1,"score":0.0},{"id":"https://openalex.org/C134306372","wikidata":"https://www.wikidata.org/wiki/Q7754","display_name":"Mathematical analysis","level":1,"score":0.0},{"id":"https://openalex.org/C205649164","wikidata":"https://www.wikidata.org/wiki/Q1071","display_name":"Geography","level":0,"score":0.0}],"mesh":[],"locations_count":2,"locations":[{"id":"doi:10.1145/1366110.1366186","is_oa":false,"landing_page_url":"https://doi.org/10.1145/1366110.1366186","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 18th ACM Great Lakes symposium on VLSI","raw_type":"proceedings-article"},{"id":"pmh:oai:HAL:hal-01301523v1","is_oa":false,"landing_page_url":"https://hal.science/hal-01301523","pdf_url":null,"source":{"id":"https://openalex.org/S4306402512","display_name":"HAL (Le Centre pour la Communication Scientifique Directe)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/I1294671590","host_organization_name":"Centre National de la Recherche Scientifique","host_organization_lineage":["https://openalex.org/I1294671590"],"host_organization_lineage_names":[],"type":"repository"},"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"GLSVLSI ACM Great Lakes Symposium on VLSI, May 2008, Orlando, Florida, United States. pp.321-326, &#x27E8;10.1145/1366110.1366186&#x27E9;","raw_type":"Conference papers"}],"best_oa_location":null,"sustainable_development_goals":[{"display_name":"Industry, innovation and infrastructure","id":"https://metadata.un.org/sdg/9","score":0.47999998927116394}],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":13,"referenced_works":["https://openalex.org/W1523051745","https://openalex.org/W1966573088","https://openalex.org/W1970296212","https://openalex.org/W2038318386","https://openalex.org/W2045726766","https://openalex.org/W2109220922","https://openalex.org/W2111756578","https://openalex.org/W2133215210","https://openalex.org/W2139637699","https://openalex.org/W2275304190","https://openalex.org/W2752885492","https://openalex.org/W3145128584","https://openalex.org/W7029321148"],"related_works":["https://openalex.org/W2111241003","https://openalex.org/W2155019192","https://openalex.org/W4390021796","https://openalex.org/W2346214237","https://openalex.org/W2537700370","https://openalex.org/W2361857689","https://openalex.org/W2102134636","https://openalex.org/W1563510876","https://openalex.org/W2945092904","https://openalex.org/W1998852263"],"abstract_inverted_index":{"This":[0],"paper":[1],"presents":[2],"an":[3,24,75],"improved":[4],"Tree-based":[5,67],"architecture":[6,40,68],"that":[7,35,65],"unifies":[8],"two":[9],"unidirectional":[10],"programmable":[11],"networks:":[12],"A":[13],"predictible":[14],"downward":[15],"network":[16,26],"based":[17,30],"on":[18,31,59],"the":[19,66],"Butter":[20],"y-Fat-Tree":[21],"topology,":[22],"and":[23,54],"upward":[25],"using":[27],"hierarchy.":[28],"Studies":[29],"Rent's":[32],"Rule":[33],"show":[34,64],"switch":[36],"requirements":[37],"in":[38,44,80],"this":[39,60],"grow":[41],"slower":[42],"than":[43],"traditional":[45],"Mesh":[46,85],"topologies.":[47],"New":[48],"tools":[49],"are":[50],"developed":[51],"to":[52],"place":[53],"route":[55],"several":[56],"benchmark":[57,72],"circuits":[58,73],"architecture.":[61,86],"Experimental":[62],"results":[63],"can":[69],"implement":[70],"MCNC":[71],"with":[74,84],"average":[76],"gain":[77],"of":[78],"54%":[79],"total":[81],"area":[82],"compared":[83]},"counts_by_year":[{"year":2022,"cited_by_count":1},{"year":2019,"cited_by_count":1},{"year":2014,"cited_by_count":1},{"year":2013,"cited_by_count":4}],"updated_date":"2026-06-11T09:08:48.828518","created_date":"2016-06-24T00:00:00"}
