{"id":"https://openalex.org/W2128566764","doi":"https://doi.org/10.1145/1366110.1366150","title":"A layout-aware analog synthesis procedure inclusive of dynamic module geometry selection","display_name":"A layout-aware analog synthesis procedure inclusive of dynamic module geometry selection","publication_year":2008,"publication_date":"2008-05-04","ids":{"openalex":"https://openalex.org/W2128566764","doi":"https://doi.org/10.1145/1366110.1366150","mag":"2128566764"},"language":"en","primary_location":{"id":"doi:10.1145/1366110.1366150","is_oa":false,"landing_page_url":"https://doi.org/10.1145/1366110.1366150","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 18th ACM Great Lakes symposium on VLSI","raw_type":"proceedings-article"},"type":"conference-paper","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5020554722","display_name":"Almitra Pradhan","orcid":null},"institutions":[{"id":"https://openalex.org/I63135867","display_name":"University of Cincinnati","ror":"https://ror.org/01e3m7079","country_code":"US","type":"education","lineage":["https://openalex.org/I63135867"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Almitra Pradhan","raw_affiliation_strings":["University of Cincinnati, Cincinnati, OH, USA","University of Cincinnati, CINCINNATI, OH, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"University of Cincinnati, Cincinnati, OH, USA","institution_ids":["https://openalex.org/I63135867"]},{"raw_affiliation_string":"University of Cincinnati, CINCINNATI, OH, USA","institution_ids":["https://openalex.org/I63135867"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5040975645","display_name":"Ranga Vemuri","orcid":"https://orcid.org/0000-0002-4903-2746"},"institutions":[{"id":"https://openalex.org/I63135867","display_name":"University of Cincinnati","ror":"https://ror.org/01e3m7079","country_code":"US","type":"education","lineage":["https://openalex.org/I63135867"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Ranga Vemuri","raw_affiliation_strings":["University of Cincinnati, Cincinnati, OH, USA","University of Cincinnati, CINCINNATI, OH, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"University of Cincinnati, Cincinnati, OH, USA","institution_ids":["https://openalex.org/I63135867"]},{"raw_affiliation_string":"University of Cincinnati, CINCINNATI, OH, USA","institution_ids":["https://openalex.org/I63135867"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":1,"corresponding_author_ids":[],"corresponding_institution_ids":["https://openalex.org/I63135867"],"apc_list":null,"apc_paid":null,"fwci":0.9489,"has_fulltext":false,"cited_by_count":7,"citation_normalized_percentile":{"value":0.71650775,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":90,"max":96},"biblio":{"volume":null,"issue":null,"first_page":"159","last_page":"162"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9983999729156494,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.995199978351593,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/schematic","display_name":"Schematic","score":0.7924245595932007},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.6873992681503296},{"id":"https://openalex.org/keywords/spice","display_name":"Spice","score":0.607401430606842},{"id":"https://openalex.org/keywords/sizing","display_name":"Sizing","score":0.5277769565582275},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.48562613129615784},{"id":"https://openalex.org/keywords/selection","display_name":"Selection (genetic algorithm)","score":0.4781016707420349},{"id":"https://openalex.org/keywords/filter","display_name":"Filter (signal processing)","score":0.45949840545654297},{"id":"https://openalex.org/keywords/integrated-circuit-layout","display_name":"Integrated circuit layout","score":0.44812506437301636},{"id":"https://openalex.org/keywords/network-topology","display_name":"Network topology","score":0.43685805797576904},{"id":"https://openalex.org/keywords/analogue-electronics","display_name":"Analogue electronics","score":0.43572214245796204},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.41645291447639465},{"id":"https://openalex.org/keywords/electronic-circuit","display_name":"Electronic circuit","score":0.40716466307640076},{"id":"https://openalex.org/keywords/topology","display_name":"Topology (electrical circuits)","score":0.3810245394706726},{"id":"https://openalex.org/keywords/integrated-circuit","display_name":"Integrated circuit","score":0.2641473710536957},{"id":"https://openalex.org/keywords/artificial-intelligence","display_name":"Artificial intelligence","score":0.15617060661315918},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.15157213807106018},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.11363571882247925}],"concepts":[{"id":"https://openalex.org/C192328126","wikidata":"https://www.wikidata.org/wiki/Q4514647","display_name":"Schematic","level":2,"score":0.7924245595932007},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6873992681503296},{"id":"https://openalex.org/C2780077345","wikidata":"https://www.wikidata.org/wiki/Q16891888","display_name":"Spice","level":2,"score":0.607401430606842},{"id":"https://openalex.org/C2777767291","wikidata":"https://www.wikidata.org/wiki/Q1080291","display_name":"Sizing","level":2,"score":0.5277769565582275},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.48562613129615784},{"id":"https://openalex.org/C81917197","wikidata":"https://www.wikidata.org/wiki/Q628760","display_name":"Selection (genetic algorithm)","level":2,"score":0.4781016707420349},{"id":"https://openalex.org/C106131492","wikidata":"https://www.wikidata.org/wiki/Q3072260","display_name":"Filter (signal processing)","level":2,"score":0.45949840545654297},{"id":"https://openalex.org/C2765594","wikidata":"https://www.wikidata.org/wiki/Q2624187","display_name":"Integrated circuit layout","level":3,"score":0.44812506437301636},{"id":"https://openalex.org/C199845137","wikidata":"https://www.wikidata.org/wiki/Q145490","display_name":"Network topology","level":2,"score":0.43685805797576904},{"id":"https://openalex.org/C29074008","wikidata":"https://www.wikidata.org/wiki/Q174925","display_name":"Analogue electronics","level":3,"score":0.43572214245796204},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.41645291447639465},{"id":"https://openalex.org/C134146338","wikidata":"https://www.wikidata.org/wiki/Q1815901","display_name":"Electronic circuit","level":2,"score":0.40716466307640076},{"id":"https://openalex.org/C184720557","wikidata":"https://www.wikidata.org/wiki/Q7825049","display_name":"Topology (electrical circuits)","level":2,"score":0.3810245394706726},{"id":"https://openalex.org/C530198007","wikidata":"https://www.wikidata.org/wiki/Q80831","display_name":"Integrated circuit","level":2,"score":0.2641473710536957},{"id":"https://openalex.org/C154945302","wikidata":"https://www.wikidata.org/wiki/Q11660","display_name":"Artificial intelligence","level":1,"score":0.15617060661315918},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.15157213807106018},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.11363571882247925},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.0},{"id":"https://openalex.org/C153349607","wikidata":"https://www.wikidata.org/wiki/Q36649","display_name":"Visual arts","level":1,"score":0.0},{"id":"https://openalex.org/C142362112","wikidata":"https://www.wikidata.org/wiki/Q735","display_name":"Art","level":0,"score":0.0},{"id":"https://openalex.org/C31972630","wikidata":"https://www.wikidata.org/wiki/Q844240","display_name":"Computer vision","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1145/1366110.1366150","is_oa":false,"landing_page_url":"https://doi.org/10.1145/1366110.1366150","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 18th ACM Great Lakes symposium on VLSI","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":8,"referenced_works":["https://openalex.org/W190668784","https://openalex.org/W1831130662","https://openalex.org/W2020446170","https://openalex.org/W2090599059","https://openalex.org/W2100529161","https://openalex.org/W2100882222","https://openalex.org/W2136848459","https://openalex.org/W2149293549"],"related_works":["https://openalex.org/W2049044818","https://openalex.org/W4353031970","https://openalex.org/W2149956247","https://openalex.org/W2119527811","https://openalex.org/W2034020979","https://openalex.org/W2147968839","https://openalex.org/W2170932855","https://openalex.org/W1625147453","https://openalex.org/W2161885327","https://openalex.org/W2017307619"],"abstract_inverted_index":{"We":[0],"propose":[1],"an":[2,100],"algorithm":[3],"for":[4,41,64],"sizing":[5],"analog":[6],"circuits":[7],"using":[8],"parasitic":[9,21,49],"aware":[10],"circuit":[11,33],"matrix":[12],"models.":[13],"A":[14],"novel":[15],"scheme":[16],"of":[17,82,95],"separating":[18],"schematic":[19],"and":[20,76,103],"models":[22,37,46],"is":[23,61],"proposed.":[24],"As":[25],"layout":[26,55,102],"details":[27],"are":[28,90],"not":[29],"abstracted":[30],"in":[31],"the":[32,35,80],"performance,":[34],"developed":[36,47],"can":[38],"be":[39],"used":[40,63],"different":[42],"module":[43,66],"geometries.":[44],"Regression":[45],"make":[48],"estimation":[50],"much":[51],"faster":[52],"than":[53],"a":[54,92],"inclusive":[56],"approach.":[57,85,105],"The":[58],"proposed":[59,84],"approach":[60],"successfully":[62],"dynamic":[65],"geometry":[67],"selection":[68],"during":[69],"synthesis.":[70],"Experiments":[71],"conducted":[72],"on":[73],"operational":[74],"amplifier":[75],"filter":[77],"topologies":[78],"demonstrate":[79],"accuracy":[81],"our":[83],"For":[86],"both":[87],"circuits,":[88],"results":[89],"within":[91],"mean":[93],"error":[94],"1":[96],"percent":[97],"compared":[98],"to":[99],"exact":[101],"spice":[104]},"counts_by_year":[{"year":2019,"cited_by_count":1},{"year":2013,"cited_by_count":2},{"year":2012,"cited_by_count":2}],"updated_date":"2026-07-29T14:22:42.915294","created_date":"2025-10-10T00:00:00"}