{"id":"https://openalex.org/W2101146398","doi":"https://doi.org/10.1145/1366110.1366138","title":"Generic sub-space algorithm for generating reduced order models of linear time varying vlsi circuits","display_name":"Generic sub-space algorithm for generating reduced order models of linear time varying vlsi circuits","publication_year":2008,"publication_date":"2008-05-04","ids":{"openalex":"https://openalex.org/W2101146398","doi":"https://doi.org/10.1145/1366110.1366138","mag":"2101146398"},"language":"en","primary_location":{"id":"doi:10.1145/1366110.1366138","is_oa":false,"landing_page_url":"https://doi.org/10.1145/1366110.1366138","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 18th ACM Great Lakes symposium on VLSI","raw_type":"proceedings-article"},"type":"conference-paper","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5111884097","display_name":"Jayanthi V R Ravindra","orcid":null},"institutions":[{"id":"https://openalex.org/I188963388","display_name":"International Institute of Information Technology","ror":"https://ror.org/02dernx73","country_code":"IN","type":"education","lineage":["https://openalex.org/I188963388"]},{"id":"https://openalex.org/I65181880","display_name":"Indian Institute of Technology Hyderabad","ror":"https://ror.org/01j4v3x97","country_code":"IN","type":"education","lineage":["https://openalex.org/I65181880"]}],"countries":["IN"],"is_corresponding":false,"raw_author_name":"Jayanthi Ravindra","raw_affiliation_strings":["International Institute of Information Technology (IIIT), Hyderabad, India","International Institute of Information Technology (IIIT), Hyderabad, India#TAB#"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"International Institute of Information Technology (IIIT), Hyderabad, India","institution_ids":["https://openalex.org/I65181880"]},{"raw_affiliation_string":"International Institute of Information Technology (IIIT), Hyderabad, India#TAB#","institution_ids":["https://openalex.org/I188963388","https://openalex.org/I65181880"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5079825929","display_name":"M. B. Srinivas","orcid":"https://orcid.org/0000-0003-1555-3639"},"institutions":[{"id":"https://openalex.org/I188963388","display_name":"International Institute of Information Technology","ror":"https://ror.org/02dernx73","country_code":"IN","type":"education","lineage":["https://openalex.org/I188963388"]},{"id":"https://openalex.org/I65181880","display_name":"Indian Institute of Technology Hyderabad","ror":"https://ror.org/01j4v3x97","country_code":"IN","type":"education","lineage":["https://openalex.org/I65181880"]}],"countries":["IN"],"is_corresponding":false,"raw_author_name":"Mandalika Srinivas","raw_affiliation_strings":["International Institute of Information Technology (IIIT), Hyderabad, India","International Institute of Information Technology (IIIT), Hyderabad, India#TAB#"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"International Institute of Information Technology (IIIT), Hyderabad, India","institution_ids":["https://openalex.org/I65181880"]},{"raw_affiliation_string":"International Institute of Information Technology (IIIT), Hyderabad, India#TAB#","institution_ids":["https://openalex.org/I188963388","https://openalex.org/I65181880"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":2,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":null,"has_fulltext":false,"cited_by_count":0,"citation_normalized_percentile":null,"cited_by_percentile_year":null,"biblio":{"volume":"9","issue":null,"first_page":"111","last_page":"114"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11206","display_name":"Model Reduction and Neural Networks","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/3109","display_name":"Statistical and Nonlinear Physics"},"field":{"id":"https://openalex.org/fields/31","display_name":"Physics and Astronomy"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11206","display_name":"Model Reduction and Neural Networks","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/3109","display_name":"Statistical and Nonlinear Physics"},"field":{"id":"https://openalex.org/fields/31","display_name":"Physics and Astronomy"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10928","display_name":"Probabilistic and Robust Engineering Design","score":0.9958999752998352,"subfield":{"id":"https://openalex.org/subfields/1804","display_name":"Statistics, Probability and Uncertainty"},"field":{"id":"https://openalex.org/fields/18","display_name":"Decision Sciences"},"domain":{"id":"https://openalex.org/domains/2","display_name":"Social Sciences"}},{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9902999997138977,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/very-large-scale-integration","display_name":"Very-large-scale integration","score":0.7569528222084045},{"id":"https://openalex.org/keywords/reduction","display_name":"Reduction (mathematics)","score":0.6872129440307617},{"id":"https://openalex.org/keywords/subspace-topology","display_name":"Subspace topology","score":0.6601413488388062},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.6247146129608154},{"id":"https://openalex.org/keywords/electronic-circuit","display_name":"Electronic circuit","score":0.5986431241035461},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.5931044220924377},{"id":"https://openalex.org/keywords/dimension","display_name":"Dimension (graph theory)","score":0.5650510191917419},{"id":"https://openalex.org/keywords/model-order-reduction","display_name":"Model order reduction","score":0.5227972865104675},{"id":"https://openalex.org/keywords/cadence","display_name":"Cadence","score":0.4906410276889801},{"id":"https://openalex.org/keywords/time-complexity","display_name":"Time complexity","score":0.4552816152572632},{"id":"https://openalex.org/keywords/switched-capacitor","display_name":"Switched capacitor","score":0.4427551031112671},{"id":"https://openalex.org/keywords/dimensionality-reduction","display_name":"Dimensionality reduction","score":0.43408384919166565},{"id":"https://openalex.org/keywords/computational-complexity-theory","display_name":"Computational complexity theory","score":0.4188512861728668},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.33987557888031006},{"id":"https://openalex.org/keywords/capacitor","display_name":"Capacitor","score":0.28342506289482117},{"id":"https://openalex.org/keywords/mathematics","display_name":"Mathematics","score":0.2585824429988861},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.13175249099731445},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.10479786992073059},{"id":"https://openalex.org/keywords/artificial-intelligence","display_name":"Artificial intelligence","score":0.08652341365814209},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.07807248830795288}],"concepts":[{"id":"https://openalex.org/C14580979","wikidata":"https://www.wikidata.org/wiki/Q876049","display_name":"Very-large-scale integration","level":2,"score":0.7569528222084045},{"id":"https://openalex.org/C111335779","wikidata":"https://www.wikidata.org/wiki/Q3454686","display_name":"Reduction (mathematics)","level":2,"score":0.6872129440307617},{"id":"https://openalex.org/C32834561","wikidata":"https://www.wikidata.org/wiki/Q660730","display_name":"Subspace topology","level":2,"score":0.6601413488388062},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6247146129608154},{"id":"https://openalex.org/C134146338","wikidata":"https://www.wikidata.org/wiki/Q1815901","display_name":"Electronic circuit","level":2,"score":0.5986431241035461},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.5931044220924377},{"id":"https://openalex.org/C33676613","wikidata":"https://www.wikidata.org/wiki/Q13415176","display_name":"Dimension (graph theory)","level":2,"score":0.5650510191917419},{"id":"https://openalex.org/C2779277453","wikidata":"https://www.wikidata.org/wiki/Q12202921","display_name":"Model order reduction","level":3,"score":0.5227972865104675},{"id":"https://openalex.org/C2777125575","wikidata":"https://www.wikidata.org/wiki/Q14088448","display_name":"Cadence","level":2,"score":0.4906410276889801},{"id":"https://openalex.org/C311688","wikidata":"https://www.wikidata.org/wiki/Q2393193","display_name":"Time complexity","level":2,"score":0.4552816152572632},{"id":"https://openalex.org/C103357873","wikidata":"https://www.wikidata.org/wiki/Q572656","display_name":"Switched capacitor","level":4,"score":0.4427551031112671},{"id":"https://openalex.org/C70518039","wikidata":"https://www.wikidata.org/wiki/Q16000077","display_name":"Dimensionality reduction","level":2,"score":0.43408384919166565},{"id":"https://openalex.org/C179799912","wikidata":"https://www.wikidata.org/wiki/Q205084","display_name":"Computational complexity theory","level":2,"score":0.4188512861728668},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.33987557888031006},{"id":"https://openalex.org/C52192207","wikidata":"https://www.wikidata.org/wiki/Q5322","display_name":"Capacitor","level":3,"score":0.28342506289482117},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.2585824429988861},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.13175249099731445},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.10479786992073059},{"id":"https://openalex.org/C154945302","wikidata":"https://www.wikidata.org/wiki/Q11660","display_name":"Artificial intelligence","level":1,"score":0.08652341365814209},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.07807248830795288},{"id":"https://openalex.org/C57493831","wikidata":"https://www.wikidata.org/wiki/Q3134666","display_name":"Projection (relational algebra)","level":2,"score":0.0},{"id":"https://openalex.org/C2524010","wikidata":"https://www.wikidata.org/wiki/Q8087","display_name":"Geometry","level":1,"score":0.0},{"id":"https://openalex.org/C202444582","wikidata":"https://www.wikidata.org/wiki/Q837863","display_name":"Pure mathematics","level":1,"score":0.0},{"id":"https://openalex.org/C165801399","wikidata":"https://www.wikidata.org/wiki/Q25428","display_name":"Voltage","level":2,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1145/1366110.1366138","is_oa":false,"landing_page_url":"https://doi.org/10.1145/1366110.1366138","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 18th ACM Great Lakes symposium on VLSI","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"id":"https://metadata.un.org/sdg/7","display_name":"Affordable and clean energy","score":0.41999998688697815}],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":15,"referenced_works":["https://openalex.org/W2001988116","https://openalex.org/W2012621058","https://openalex.org/W2031151301","https://openalex.org/W2079063703","https://openalex.org/W2099752485","https://openalex.org/W2112354112","https://openalex.org/W2116017330","https://openalex.org/W2122608783","https://openalex.org/W2123947147","https://openalex.org/W2127062440","https://openalex.org/W2134132575","https://openalex.org/W2136679308","https://openalex.org/W2146350805","https://openalex.org/W2149246659","https://openalex.org/W2163626738"],"related_works":["https://openalex.org/W4289538008","https://openalex.org/W3186427148","https://openalex.org/W2138282914","https://openalex.org/W2065850627","https://openalex.org/W2017012638","https://openalex.org/W2071885361","https://openalex.org/W1966793535","https://openalex.org/W1964447062","https://openalex.org/W2088265144","https://openalex.org/W3178635520"],"abstract_inverted_index":{"We":[0,110],"present":[1,112],"an":[2],"algorithm":[3],"for":[4],"reducing":[5,32],"large":[6],"VLSI":[7],"circuits":[8],"to":[9,39,114],"much":[10],"smaller":[11],"ones":[12],"with":[13,96,128],"similar":[14],"input-output":[15],"behavior.":[16],"A":[17],"key":[18],"feature":[19],"of":[20,31,72,124,126,131],"our":[21],"method,":[22],"called":[23],"generic":[24],"subspace,":[25],"is":[26,29,58],"that":[27,87],"it":[28,38],"capable":[30],"linear":[33,67],"time-varying":[34],"systems.":[35],"This":[36],"enables":[37],"capture":[40],"frequency-translation":[41],"and":[42,54,121],"sampling":[43],"behavior,":[44],"important":[45],"in":[46,108],"communication":[47],"subsystems":[48],"such":[49],"as":[50],"mixers,":[51],"RF":[52,115],"components":[53],"switched-capacitor":[55],"filters.":[56],"Reduction":[57],"obtained":[59],"by":[60,66],"projecting":[61],"the":[62,88,101],"original":[63],"system":[64],"described":[65],"differential":[68],"equations":[69],"into":[70],"subspace":[71],"a":[73],"lower":[74],"dimension.":[75],"Experiments":[76],"have":[77],"been":[78],"carried":[79],"out":[80],"using":[81],"Cadence":[82],"Design":[83],"Simulator":[84],"which":[85],"indicates":[86],"proposed":[89],"sub-space":[90],"technique":[91],"achieves":[92],"more":[93],"%":[94],"reduction":[95,105],"less":[97],"CPU":[98],"time":[99],"than":[100],"other":[102],"model":[103],"order":[104],"techniques":[106],"existing":[107],"literature.":[109],"also":[111],"applications":[113],"circuit":[116],"subsystems,":[117],"obtaining":[118],"size":[119],"reductions":[120],"evaluation":[122],"speedups":[123],"orders":[125],"magnitude":[127],"insignificant":[129],"loss":[130],"accuracy.":[132]},"counts_by_year":[],"updated_date":"2026-07-22T07:51:19.307946","created_date":"2025-10-10T00:00:00"}