{"id":"https://openalex.org/W2098800716","doi":"https://doi.org/10.1145/1366110.1366118","title":"Considering possible opens in non-tree topology wire delay calculation","display_name":"Considering possible opens in non-tree topology wire delay calculation","publication_year":2008,"publication_date":"2008-05-04","ids":{"openalex":"https://openalex.org/W2098800716","doi":"https://doi.org/10.1145/1366110.1366118","mag":"2098800716"},"language":"en","primary_location":{"id":"doi:10.1145/1366110.1366118","is_oa":false,"landing_page_url":"https://doi.org/10.1145/1366110.1366118","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 18th ACM Great Lakes symposium on VLSI","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5055278608","display_name":"P. Panitz","orcid":null},"institutions":[{"id":"https://openalex.org/I114112103","display_name":"Leibniz University Hannover","ror":"https://ror.org/0304hq317","country_code":"DE","type":"education","lineage":["https://openalex.org/I114112103"]}],"countries":["DE"],"is_corresponding":false,"raw_author_name":"Philipp Panitz","raw_affiliation_strings":["Leibniz University of Hannover, Hannover, Germany"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Leibniz University of Hannover, Hannover, Germany","institution_ids":["https://openalex.org/I114112103"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5010238994","display_name":"Markus Olbrich","orcid":"https://orcid.org/0000-0001-9851-5982"},"institutions":[{"id":"https://openalex.org/I114112103","display_name":"Leibniz University Hannover","ror":"https://ror.org/0304hq317","country_code":"DE","type":"education","lineage":["https://openalex.org/I114112103"]}],"countries":["DE"],"is_corresponding":false,"raw_author_name":"Markus Olbrich","raw_affiliation_strings":["Leibniz University of Hannover, Hannover, Germany"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Leibniz University of Hannover, Hannover, Germany","institution_ids":["https://openalex.org/I114112103"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5057367287","display_name":"Erich Barke","orcid":"https://orcid.org/0000-0001-5744-2940"},"institutions":[{"id":"https://openalex.org/I114112103","display_name":"Leibniz University Hannover","ror":"https://ror.org/0304hq317","country_code":"DE","type":"education","lineage":["https://openalex.org/I114112103"]}],"countries":["DE"],"is_corresponding":false,"raw_author_name":"Erich Barke","raw_affiliation_strings":["Leibniz University of Hannover, Hannover, Germany"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Leibniz University of Hannover, Hannover, Germany","institution_ids":["https://openalex.org/I114112103"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5011504360","display_name":"Markus J. Buehler","orcid":"https://orcid.org/0000-0002-4173-9659"},"institutions":[{"id":"https://openalex.org/I1341412227","display_name":"IBM (United States)","ror":"https://ror.org/05hh8d621","country_code":"US","type":"company","lineage":["https://openalex.org/I1341412227"]},{"id":"https://openalex.org/I4210095996","display_name":"IBM (Germany)","ror":"https://ror.org/00pm7rm97","country_code":"DE","type":"company","lineage":["https://openalex.org/I1341412227","https://openalex.org/I4210095996"]}],"countries":["DE","US"],"is_corresponding":false,"raw_author_name":"Markus Buehler","raw_affiliation_strings":["IBM Deutschland Entwicklung GmbH, Boeblingen, Germany","IBM Deutschland Entwicklung GmbH, Boeblingen, Germany#TAB#"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"IBM Deutschland Entwicklung GmbH, Boeblingen, Germany","institution_ids":["https://openalex.org/I4210095996"]},{"raw_affiliation_string":"IBM Deutschland Entwicklung GmbH, Boeblingen, Germany#TAB#","institution_ids":["https://openalex.org/I1341412227"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5110266665","display_name":"J. Koehl","orcid":null},"institutions":[{"id":"https://openalex.org/I1341412227","display_name":"IBM (United States)","ror":"https://ror.org/05hh8d621","country_code":"US","type":"company","lineage":["https://openalex.org/I1341412227"]},{"id":"https://openalex.org/I4210095996","display_name":"IBM (Germany)","ror":"https://ror.org/00pm7rm97","country_code":"DE","type":"company","lineage":["https://openalex.org/I1341412227","https://openalex.org/I4210095996"]}],"countries":["DE","US"],"is_corresponding":false,"raw_author_name":"Juergen Koehl","raw_affiliation_strings":["IBM Deutschland Entwicklung GmbH, Boeblingen, Germany","IBM Deutschland Entwicklung GmbH, Boeblingen, Germany#TAB#"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"IBM Deutschland Entwicklung GmbH, Boeblingen, Germany","institution_ids":["https://openalex.org/I4210095996"]},{"raw_affiliation_string":"IBM Deutschland Entwicklung GmbH, Boeblingen, Germany#TAB#","institution_ids":["https://openalex.org/I1341412227"]}]}],"institutions":[],"countries_distinct_count":2,"institutions_distinct_count":5,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":1.0175,"has_fulltext":false,"cited_by_count":6,"citation_normalized_percentile":{"value":0.78501261,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":90,"max":96},"biblio":{"volume":null,"issue":null,"first_page":"17","last_page":"22"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/robustness","display_name":"Robustness (evolution)","score":0.7128435373306274},{"id":"https://openalex.org/keywords/network-topology","display_name":"Network topology","score":0.6194723844528198},{"id":"https://openalex.org/keywords/topology","display_name":"Topology (electrical circuits)","score":0.6185007691383362},{"id":"https://openalex.org/keywords/parametric-statistics","display_name":"Parametric statistics","score":0.5590561628341675},{"id":"https://openalex.org/keywords/metric","display_name":"Metric (unit)","score":0.5589317679405212},{"id":"https://openalex.org/keywords/net","display_name":"Net (polyhedron)","score":0.5285186767578125},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.5229792594909668},{"id":"https://openalex.org/keywords/elmore-delay","display_name":"Elmore delay","score":0.4400521218776703},{"id":"https://openalex.org/keywords/mathematics","display_name":"Mathematics","score":0.3254814147949219},{"id":"https://openalex.org/keywords/control-theory","display_name":"Control theory (sociology)","score":0.32039546966552734},{"id":"https://openalex.org/keywords/delay-calculation","display_name":"Delay calculation","score":0.24182233214378357},{"id":"https://openalex.org/keywords/propagation-delay","display_name":"Propagation delay","score":0.18587905168533325},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.12796887755393982},{"id":"https://openalex.org/keywords/computer-network","display_name":"Computer network","score":0.12427523732185364}],"concepts":[{"id":"https://openalex.org/C63479239","wikidata":"https://www.wikidata.org/wiki/Q7353546","display_name":"Robustness (evolution)","level":3,"score":0.7128435373306274},{"id":"https://openalex.org/C199845137","wikidata":"https://www.wikidata.org/wiki/Q145490","display_name":"Network topology","level":2,"score":0.6194723844528198},{"id":"https://openalex.org/C184720557","wikidata":"https://www.wikidata.org/wiki/Q7825049","display_name":"Topology (electrical circuits)","level":2,"score":0.6185007691383362},{"id":"https://openalex.org/C117251300","wikidata":"https://www.wikidata.org/wiki/Q1849855","display_name":"Parametric statistics","level":2,"score":0.5590561628341675},{"id":"https://openalex.org/C176217482","wikidata":"https://www.wikidata.org/wiki/Q860554","display_name":"Metric (unit)","level":2,"score":0.5589317679405212},{"id":"https://openalex.org/C14166107","wikidata":"https://www.wikidata.org/wiki/Q253829","display_name":"Net (polyhedron)","level":2,"score":0.5285186767578125},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.5229792594909668},{"id":"https://openalex.org/C84434228","wikidata":"https://www.wikidata.org/wiki/Q4531332","display_name":"Elmore delay","level":4,"score":0.4400521218776703},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.3254814147949219},{"id":"https://openalex.org/C47446073","wikidata":"https://www.wikidata.org/wiki/Q5165890","display_name":"Control theory (sociology)","level":3,"score":0.32039546966552734},{"id":"https://openalex.org/C174086752","wikidata":"https://www.wikidata.org/wiki/Q5253471","display_name":"Delay calculation","level":3,"score":0.24182233214378357},{"id":"https://openalex.org/C90806461","wikidata":"https://www.wikidata.org/wiki/Q1144416","display_name":"Propagation delay","level":2,"score":0.18587905168533325},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.12796887755393982},{"id":"https://openalex.org/C31258907","wikidata":"https://www.wikidata.org/wiki/Q1301371","display_name":"Computer network","level":1,"score":0.12427523732185364},{"id":"https://openalex.org/C2524010","wikidata":"https://www.wikidata.org/wiki/Q8087","display_name":"Geometry","level":1,"score":0.0},{"id":"https://openalex.org/C104317684","wikidata":"https://www.wikidata.org/wiki/Q7187","display_name":"Gene","level":2,"score":0.0},{"id":"https://openalex.org/C114614502","wikidata":"https://www.wikidata.org/wiki/Q76592","display_name":"Combinatorics","level":1,"score":0.0},{"id":"https://openalex.org/C21547014","wikidata":"https://www.wikidata.org/wiki/Q1423657","display_name":"Operations management","level":1,"score":0.0},{"id":"https://openalex.org/C185592680","wikidata":"https://www.wikidata.org/wiki/Q2329","display_name":"Chemistry","level":0,"score":0.0},{"id":"https://openalex.org/C154945302","wikidata":"https://www.wikidata.org/wiki/Q11660","display_name":"Artificial intelligence","level":1,"score":0.0},{"id":"https://openalex.org/C55493867","wikidata":"https://www.wikidata.org/wiki/Q7094","display_name":"Biochemistry","level":1,"score":0.0},{"id":"https://openalex.org/C105795698","wikidata":"https://www.wikidata.org/wiki/Q12483","display_name":"Statistics","level":1,"score":0.0},{"id":"https://openalex.org/C2775924081","wikidata":"https://www.wikidata.org/wiki/Q55608371","display_name":"Control (management)","level":2,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1145/1366110.1366118","is_oa":false,"landing_page_url":"https://doi.org/10.1145/1366110.1366118","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 18th ACM Great Lakes symposium on VLSI","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"id":"https://metadata.un.org/sdg/9","score":0.4300000071525574,"display_name":"Industry, innovation and infrastructure"}],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":17,"referenced_works":["https://openalex.org/W571322228","https://openalex.org/W1578824783","https://openalex.org/W1984588379","https://openalex.org/W2069441127","https://openalex.org/W2085394932","https://openalex.org/W2107180895","https://openalex.org/W2113959782","https://openalex.org/W2122658077","https://openalex.org/W2126226073","https://openalex.org/W2128054043","https://openalex.org/W2141382801","https://openalex.org/W2163626738","https://openalex.org/W2167285764","https://openalex.org/W2168150082","https://openalex.org/W2407658200","https://openalex.org/W2542641932","https://openalex.org/W6616380998"],"related_works":["https://openalex.org/W2166251094","https://openalex.org/W4245364671","https://openalex.org/W2086497127","https://openalex.org/W1514127200","https://openalex.org/W2625944369","https://openalex.org/W1691923927","https://openalex.org/W2153558271","https://openalex.org/W4237831527","https://openalex.org/W2113537658","https://openalex.org/W2367065412"],"abstract_inverted_index":{"Non-tree":[0],"routing":[1],"experiences":[2],"an":[3,62,72,81,121],"increasing":[4],"interest":[5],"as":[6],"technology":[7],"scales":[8],"into":[9],"the":[10,19,29,54,69,75,78,117,125,137,141,155,160],"nanometer":[11],"range.":[12],"Via":[13],"and":[14,93],"wire":[15],"opens":[16],"have":[17],"become":[18],"main":[20],"yield":[21],"detractors":[22],"considering":[23,140],"random":[24],"spot":[25],"defects":[26,45],"due":[27],"to":[28,114],"additive":[30],"manufacturing":[31],"process":[32],"of":[33,56,71,80,130,157],"copper":[34],"wires.":[35],"Wiring":[36],"networks":[37],"containing":[38],"loops":[39,57,132,158],"offer":[40],"some":[41],"robustness":[42],"against":[43],"open":[44,82,122],"which":[46,99],"increases":[47],"functional":[48,88],"yield.":[49],"State-of-the-art":[50],"delay":[51,76,104,119,139,143,150],"calculation":[52],"enables":[53],"treatment":[55],"but":[58],"does":[59],"not":[60,84],"provide":[61,134],"adequate":[63],"solution":[64],"for":[65],"timing":[66],"analysis":[67],"in":[68,77,124,148,159],"presence":[70,79],"open.":[73],"If":[74],"is":[83,100,154],"properly":[85],"analyzed,":[86],"a":[87,96,111],"fail":[89,98],"will":[90],"be":[91,146],"masked":[92],"replaced":[94],"by":[95],"parametric":[97],"only":[101],"detectable":[102],"applying":[103],"testing.":[105],"In":[106],"this":[107],"paper":[108],"we":[109,133],"present":[110],"new":[112],"method":[113],"rapidly":[115],"calculate":[116],"maximum":[118],"if":[120],"occurs":[123],"net.":[126,161],"For":[127],"topologies":[128],"consisting":[129],"non-adjacent":[131],"proof":[135],"that":[136],"worst":[138],"Elmore":[142],"metric":[144],"can":[145],"found":[147],"2N+1":[149],"calculations,":[151],"whereas":[152],"N":[153],"number":[156]},"counts_by_year":[{"year":2019,"cited_by_count":1},{"year":2012,"cited_by_count":2}],"updated_date":"2026-06-11T09:08:48.828518","created_date":"2025-10-10T00:00:00"}