{"id":"https://openalex.org/W1986314250","doi":"https://doi.org/10.1145/1363686.1364037","title":"VHDL vs. Bluespec system verilog","display_name":"VHDL vs. Bluespec system verilog","publication_year":2008,"publication_date":"2008-03-16","ids":{"openalex":"https://openalex.org/W1986314250","doi":"https://doi.org/10.1145/1363686.1364037","mag":"1986314250"},"language":"en","primary_location":{"id":"doi:10.1145/1363686.1364037","is_oa":false,"landing_page_url":"https://doi.org/10.1145/1363686.1364037","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 2008 ACM symposium on Applied computing","raw_type":"proceedings-article"},"type":"conference-paper","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5076838369","display_name":"Flavius Gruian","orcid":"https://orcid.org/0000-0003-1739-3384"},"institutions":[{"id":"https://openalex.org/I187531555","display_name":"Lund University","ror":"https://ror.org/012a77v79","country_code":"SE","type":"education","lineage":["https://openalex.org/I187531555"]}],"countries":["SE"],"is_corresponding":false,"raw_author_name":"Flavius Gruian","raw_affiliation_strings":["Lund University, Lund, Sweden"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Lund University, Lund, Sweden","institution_ids":["https://openalex.org/I187531555"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5024851547","display_name":"Mark Westmijze","orcid":null},"institutions":[{"id":"https://openalex.org/I94624287","display_name":"University of Twente","ror":"https://ror.org/006hf6230","country_code":"NL","type":"education","lineage":["https://openalex.org/I94624287"]}],"countries":["NL"],"is_corresponding":false,"raw_author_name":"Mark Westmijze","raw_affiliation_strings":["University of Twente, Enschede, The Netherlands"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"University of Twente, Enschede, The Netherlands","institution_ids":["https://openalex.org/I94624287"]}]}],"institutions":[],"countries_distinct_count":2,"institutions_distinct_count":2,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":1.3152,"has_fulltext":false,"cited_by_count":19,"citation_normalized_percentile":{"value":0.7886608,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":90,"max":98},"biblio":{"volume":null,"issue":null,"first_page":"1492","last_page":"1497"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10933","display_name":"Real-Time Systems Scheduling","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.846295952796936},{"id":"https://openalex.org/keywords/verilog","display_name":"Verilog","score":0.7751235961914062},{"id":"https://openalex.org/keywords/vhdl","display_name":"VHDL","score":0.7295982241630554},{"id":"https://openalex.org/keywords/java","display_name":"Java","score":0.6137034893035889},{"id":"https://openalex.org/keywords/garbage-collection","display_name":"Garbage collection","score":0.5405693054199219},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.5043331384658813},{"id":"https://openalex.org/keywords/programming-language","display_name":"Programming language","score":0.49277856945991516},{"id":"https://openalex.org/keywords/operating-system","display_name":"Operating system","score":0.4412339925765991},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.40306928753852844},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.258513867855072},{"id":"https://openalex.org/keywords/garbage","display_name":"Garbage","score":0.10922789573669434}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.846295952796936},{"id":"https://openalex.org/C2779030575","wikidata":"https://www.wikidata.org/wiki/Q827773","display_name":"Verilog","level":3,"score":0.7751235961914062},{"id":"https://openalex.org/C36941000","wikidata":"https://www.wikidata.org/wiki/Q209455","display_name":"VHDL","level":3,"score":0.7295982241630554},{"id":"https://openalex.org/C548217200","wikidata":"https://www.wikidata.org/wiki/Q251","display_name":"Java","level":2,"score":0.6137034893035889},{"id":"https://openalex.org/C105122174","wikidata":"https://www.wikidata.org/wiki/Q322202","display_name":"Garbage collection","level":3,"score":0.5405693054199219},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.5043331384658813},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.49277856945991516},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.4412339925765991},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.40306928753852844},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.258513867855072},{"id":"https://openalex.org/C75403996","wikidata":"https://www.wikidata.org/wiki/Q5521979","display_name":"Garbage","level":2,"score":0.10922789573669434}],"mesh":[],"locations_count":4,"locations":[{"id":"doi:10.1145/1363686.1364037","is_oa":false,"landing_page_url":"https://doi.org/10.1145/1363686.1364037","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 2008 ACM symposium on Applied computing","raw_type":"proceedings-article"},{"id":"pmh:oai:ris.utwente.nl:openaire_cris_publications/135ef35c-c9b4-4d15-9900-45c0c63635f3","is_oa":false,"landing_page_url":"https://research.utwente.nl/en/publications/135ef35c-c9b4-4d15-9900-45c0c63635f3","pdf_url":null,"source":{"id":"https://openalex.org/S4406922991","display_name":"University of Twente Research Information","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":null,"host_organization_name":null,"host_organization_lineage":[],"host_organization_lineage_names":[],"type":"repository"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Gruian, F & Westmijze, M 2008, VHDL vs. Bluespec system verilog: a case study on a Java embedded architecture. in SAC '08 : The 2008 ACM Symposium on Applied Computing, Fortaleza, Ceara, Brazil - March 16-20, 2008. Association for Computing Machinery, New York, NY, USA, pp. 1492-1497, 23rd Annual ACM Symposium on Applied Computing, SAC 2008, Fortaleza, Brazil, 16/03/08. https://doi.org/10.1145/1363686.1364037","raw_type":"info:eu-repo/semantics/conferenceObject"},{"id":"pmh:oai:lup.lub.lu.se:77fc25f6-3f7b-4f6f-862a-618713db1ffa","is_oa":false,"landing_page_url":"https://lup.lub.lu.se/record/622816","pdf_url":null,"source":{"id":"https://openalex.org/S4306400536","display_name":"Lund University Publications (Lund University)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/I187531555","host_organization_name":"Lund University","host_organization_lineage":["https://openalex.org/I187531555"],"host_organization_lineage_names":[],"type":"repository"},"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":null,"raw_type":"info:eu-repo/semantics/conferencePaper"},{"id":"pmh:oai:ris.utwente.nl:publications/135ef35c-c9b4-4d15-9900-45c0c63635f3","is_oa":false,"landing_page_url":"http://eprints.eemcs.utwente.nl/secure2/12984/01/p1492-gruian.pdf","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"","raw_type":""}],"best_oa_location":null,"sustainable_development_goals":[{"score":0.44999998807907104,"display_name":"Industry, innovation and infrastructure","id":"https://metadata.un.org/sdg/9"}],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":18,"referenced_works":["https://openalex.org/W136446312","https://openalex.org/W1521915012","https://openalex.org/W1550131357","https://openalex.org/W1569551987","https://openalex.org/W1606583766","https://openalex.org/W1683919907","https://openalex.org/W1805422776","https://openalex.org/W1989016096","https://openalex.org/W2014663396","https://openalex.org/W2098682737","https://openalex.org/W2123694710","https://openalex.org/W2139020255","https://openalex.org/W2161614117","https://openalex.org/W3023634467","https://openalex.org/W4214633034","https://openalex.org/W6633991648","https://openalex.org/W6634941054","https://openalex.org/W7043665758"],"related_works":["https://openalex.org/W2005091774","https://openalex.org/W2114459515","https://openalex.org/W2060525997","https://openalex.org/W2111408175","https://openalex.org/W1761969858","https://openalex.org/W78782492","https://openalex.org/W2122949436","https://openalex.org/W1043594576","https://openalex.org/W190963477","https://openalex.org/W2391854357"],"abstract_inverted_index":{"This":[0],"paper":[1],"compares":[2],"two":[3,87],"hardware":[4],"design":[5,88,106],"flows,":[6],"based":[7,30],"on":[8,12,23,31,104],"the":[9,16,24,74,111,129,139],"classic":[10,126],"VHDL":[11],"one":[13],"side":[14],"and":[15,45,63,100],"relatively":[17],"new":[18,112],"Blue-spec":[19],"System":[20],"Verilog":[21],"(BSV)":[22],"other":[25],"side.":[26],"The":[27,50,86],"comparison":[28,121],"is":[29,52],"a":[32,36,41,46,53,82],"case":[33],"study":[34],"of":[35,95],"Java":[37,42],"embedded":[38],"architecture,":[39],"comprising":[40],"native":[43],"processor":[44,51,57],"memory":[47,70,78],"management":[48,71],"unit.":[49],"micro-programmed,":[54],"pipelined,":[55],"Java-optimized":[56],"(JOP),":[58],"initially":[59],"written":[60],"in":[61,120,138],"VHDL,":[62],"its":[64],"BSV":[65],"re-designed":[66],"match":[67],"BLUEJEP.":[68],"Its":[69],"unit":[72],"implements":[73],"bytecodes":[75],"dealing":[76],"with":[77,81],"allocation,":[79],"along":[80],"mark-compact":[83],"garbage":[84],"collector.":[85],"flows":[89],"are":[90],"examined":[91],"from":[92],"several":[93],"points":[94],"view,":[96],"including":[97],"both":[98],"quantitative":[99],"qualitative":[101],"measures.":[102],"Based":[103],"this":[105],"experience,":[107],"we":[108],"conclude":[109],"that":[110,132],"high-abstraction":[113],"level":[114,125],"languages,":[115],"such":[116],"as":[117],"BSV,":[118],"offer":[119],"to":[122],"register-transfer":[123],"(RT)":[124],"approaches":[127],"roughly":[128],"same":[130],"trade-offs":[131],"C++":[133],"offers":[134],"vs.":[135],"assembly":[136],"language":[137],"software":[140],"world.":[141]},"counts_by_year":[{"year":2024,"cited_by_count":1},{"year":2017,"cited_by_count":1},{"year":2016,"cited_by_count":1},{"year":2015,"cited_by_count":2},{"year":2014,"cited_by_count":3},{"year":2012,"cited_by_count":4}],"updated_date":"2026-07-29T14:22:42.915294","created_date":"2025-10-10T00:00:00"}