{"id":"https://openalex.org/W2149377744","doi":"https://doi.org/10.1145/1363686.1364035","title":"Exploiting program cyclic behavior to reduce memory latency in embedded processors","display_name":"Exploiting program cyclic behavior to reduce memory latency in embedded processors","publication_year":2008,"publication_date":"2008-03-16","ids":{"openalex":"https://openalex.org/W2149377744","doi":"https://doi.org/10.1145/1363686.1364035","mag":"2149377744"},"language":"en","primary_location":{"id":"doi:10.1145/1363686.1364035","is_oa":false,"landing_page_url":"https://doi.org/10.1145/1363686.1364035","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 2008 ACM symposium on Applied computing","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5012159659","display_name":"Ehsan Atoofian","orcid":"https://orcid.org/0000-0002-1662-5334"},"institutions":[{"id":"https://openalex.org/I212119943","display_name":"University of Victoria","ror":"https://ror.org/04s5mat29","country_code":"CA","type":"education","lineage":["https://openalex.org/I212119943"]}],"countries":["CA"],"is_corresponding":false,"raw_author_name":"Ehsan Atoofian","raw_affiliation_strings":["University of Victoria, Victoria BC, Canada"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"University of Victoria, Victoria BC, Canada","institution_ids":["https://openalex.org/I212119943"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5000153604","display_name":"Amirali Baniasadi","orcid":null},"institutions":[{"id":"https://openalex.org/I212119943","display_name":"University of Victoria","ror":"https://ror.org/04s5mat29","country_code":"CA","type":"education","lineage":["https://openalex.org/I212119943"]}],"countries":["CA"],"is_corresponding":false,"raw_author_name":"Amirali Baniasadi","raw_affiliation_strings":["University of Victoria, Victoria BC, Canada"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"University of Victoria, Victoria BC, Canada","institution_ids":["https://openalex.org/I212119943"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":1,"corresponding_author_ids":[],"corresponding_institution_ids":["https://openalex.org/I212119943"],"apc_list":null,"apc_paid":null,"fwci":0.3452,"has_fulltext":false,"cited_by_count":1,"citation_normalized_percentile":{"value":0.71131762,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":null,"issue":null,"first_page":"1482","last_page":"1486"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.9997000098228455,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9994999766349792,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.774375319480896},{"id":"https://openalex.org/keywords/latency","display_name":"Latency (audio)","score":0.7245545983314514},{"id":"https://openalex.org/keywords/cas-latency","display_name":"CAS latency","score":0.6025719046592712},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.6010594964027405},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.45240291953086853},{"id":"https://openalex.org/keywords/storage-management","display_name":"Storage management","score":0.42381638288497925},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.31860893964767456},{"id":"https://openalex.org/keywords/memory-controller","display_name":"Memory controller","score":0.30215901136398315},{"id":"https://openalex.org/keywords/operating-system","display_name":"Operating system","score":0.2733972370624542},{"id":"https://openalex.org/keywords/semiconductor-memory","display_name":"Semiconductor memory","score":0.19204995036125183}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.774375319480896},{"id":"https://openalex.org/C82876162","wikidata":"https://www.wikidata.org/wiki/Q17096504","display_name":"Latency (audio)","level":2,"score":0.7245545983314514},{"id":"https://openalex.org/C189930140","wikidata":"https://www.wikidata.org/wiki/Q1112878","display_name":"CAS latency","level":4,"score":0.6025719046592712},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.6010594964027405},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.45240291953086853},{"id":"https://openalex.org/C2984984529","wikidata":"https://www.wikidata.org/wiki/Q7619925","display_name":"Storage management","level":2,"score":0.42381638288497925},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.31860893964767456},{"id":"https://openalex.org/C100800780","wikidata":"https://www.wikidata.org/wiki/Q1175867","display_name":"Memory controller","level":3,"score":0.30215901136398315},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.2733972370624542},{"id":"https://openalex.org/C98986596","wikidata":"https://www.wikidata.org/wiki/Q1143031","display_name":"Semiconductor memory","level":2,"score":0.19204995036125183},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.0}],"mesh":[],"locations_count":2,"locations":[{"id":"doi:10.1145/1363686.1364035","is_oa":false,"landing_page_url":"https://doi.org/10.1145/1363686.1364035","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 2008 ACM symposium on Applied computing","raw_type":"proceedings-article"},{"id":"pmh:oai:CiteSeerX.psu:10.1.1.537.2922","is_oa":false,"landing_page_url":"http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.537.2922","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"http://www.ece.uvic.ca/~amiralib/publications/sac08.pdf","raw_type":"text"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":12,"referenced_works":["https://openalex.org/W1569032152","https://openalex.org/W1686420892","https://openalex.org/W1983096721","https://openalex.org/W2097215759","https://openalex.org/W2110815624","https://openalex.org/W2113002954","https://openalex.org/W2115172404","https://openalex.org/W2123306627","https://openalex.org/W2128315927","https://openalex.org/W2149904390","https://openalex.org/W2159448567","https://openalex.org/W4292169167"],"related_works":["https://openalex.org/W2082939521","https://openalex.org/W2547220881","https://openalex.org/W1603816627","https://openalex.org/W2532617734","https://openalex.org/W2132401245","https://openalex.org/W3089341786","https://openalex.org/W2056138949","https://openalex.org/W1976244802","https://openalex.org/W2389333520","https://openalex.org/W2170496111"],"abstract_inverted_index":{"In":[0],"this":[1],"work":[2],"we":[3],"modify":[4],"the":[5],"conventional":[6],"row":[7,28,44],"buffer":[8,45],"allocation":[9],"mechanism":[10],"used":[11],"in":[12],"DDR2":[13],"SDRAM":[14],"banks":[15,32],"to":[16,30],"improve":[17],"average":[18],"memory":[19],"latency":[20],"and":[21,34,42],"overall":[22],"processor":[23],"performance.":[24],"Our":[25],"method":[26],"assigns":[27],"buffers":[29],"different":[31],"dynamically":[33],"by":[35],"taking":[36],"into":[37],"account":[38],"program":[39],"cyclic":[40],"behavior":[41],"bank":[43],"demand.":[46]},"counts_by_year":[],"updated_date":"2026-06-26T08:34:08.712188","created_date":"2025-10-10T00:00:00"}
