{"id":"https://openalex.org/W2108736483","doi":"https://doi.org/10.1145/1362622.1362652","title":"Scaling performance of interior-point method on large-scale chip multiprocessor system","display_name":"Scaling performance of interior-point method on large-scale chip multiprocessor system","publication_year":2007,"publication_date":"2007-11-10","ids":{"openalex":"https://openalex.org/W2108736483","doi":"https://doi.org/10.1145/1362622.1362652","mag":"2108736483"},"language":"en","primary_location":{"id":"doi:10.1145/1362622.1362652","is_oa":false,"landing_page_url":"https://doi.org/10.1145/1362622.1362652","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 2007 ACM/IEEE conference on Supercomputing","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5007892541","display_name":"Mikhail Smelyanskiy","orcid":"https://orcid.org/0000-0002-2433-6110"},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":true,"raw_author_name":"Mikhail Smelyanskiy","raw_affiliation_strings":["Microprocessor Technology Labs, Intel"],"affiliations":[{"raw_affiliation_string":"Microprocessor Technology Labs, Intel","institution_ids":["https://openalex.org/I1343180700"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5109971580","display_name":"Victor W. Lee","orcid":null},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Victor W Lee","raw_affiliation_strings":["Microprocessor Technology Labs, Intel"],"affiliations":[{"raw_affiliation_string":"Microprocessor Technology Labs, Intel","institution_ids":["https://openalex.org/I1343180700"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5100374575","display_name":"Daehyun Kim","orcid":"https://orcid.org/0000-0002-5582-3579"},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Daehyun Kim","raw_affiliation_strings":["Microprocessor Technology Labs, Intel"],"affiliations":[{"raw_affiliation_string":"Microprocessor Technology Labs, Intel","institution_ids":["https://openalex.org/I1343180700"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5047809126","display_name":"Anthony D. Nguyen","orcid":null},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Anthony D Nguyen","raw_affiliation_strings":["Microprocessor Technology Labs, Intel"],"affiliations":[{"raw_affiliation_string":"Microprocessor Technology Labs, Intel","institution_ids":["https://openalex.org/I1343180700"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5032238070","display_name":"Pradeep Dubey","orcid":"https://orcid.org/0000-0001-5853-0619"},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Pradeep Dubey","raw_affiliation_strings":["Microprocessor Technology Labs, Intel"],"affiliations":[{"raw_affiliation_string":"Microprocessor Technology Labs, Intel","institution_ids":["https://openalex.org/I1343180700"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":5,"corresponding_author_ids":["https://openalex.org/A5007892541"],"corresponding_institution_ids":["https://openalex.org/I1343180700"],"apc_list":null,"apc_paid":null,"fwci":1.8716,"has_fulltext":false,"cited_by_count":9,"citation_normalized_percentile":{"value":0.85932169,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":90,"max":96},"biblio":{"volume":null,"issue":null,"first_page":"1","last_page":"11"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10792","display_name":"Matrix Theory and Algorithms","score":0.9997000098228455,"subfield":{"id":"https://openalex.org/subfields/1703","display_name":"Computational Theory and Mathematics"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10792","display_name":"Matrix Theory and Algorithms","score":0.9997000098228455,"subfield":{"id":"https://openalex.org/subfields/1703","display_name":"Computational Theory and Mathematics"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11697","display_name":"Numerical Methods and Algorithms","score":0.9987999796867371,"subfield":{"id":"https://openalex.org/subfields/1703","display_name":"Computational Theory and Mathematics"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9986000061035156,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/scalability","display_name":"Scalability","score":0.8236683011054993},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.8133112192153931},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.7859236001968384},{"id":"https://openalex.org/keywords/multiprocessing","display_name":"Multiprocessing","score":0.7345020771026611},{"id":"https://openalex.org/keywords/parallelism","display_name":"Parallelism (grammar)","score":0.7226472496986389},{"id":"https://openalex.org/keywords/scale","display_name":"Scale (ratio)","score":0.5750285387039185},{"id":"https://openalex.org/keywords/exploit","display_name":"Exploit","score":0.5544626712799072},{"id":"https://openalex.org/keywords/scaling","display_name":"Scaling","score":0.5389993190765381},{"id":"https://openalex.org/keywords/computation","display_name":"Computation","score":0.5376698970794678},{"id":"https://openalex.org/keywords/point","display_name":"Point (geometry)","score":0.5211641788482666},{"id":"https://openalex.org/keywords/linear-algebra","display_name":"Linear algebra","score":0.4608108699321747},{"id":"https://openalex.org/keywords/interior-point-method","display_name":"Interior point method","score":0.46002310514450073},{"id":"https://openalex.org/keywords/task-parallelism","display_name":"Task parallelism","score":0.4555962085723877},{"id":"https://openalex.org/keywords/chip","display_name":"Chip","score":0.4204564392566681},{"id":"https://openalex.org/keywords/computational-science","display_name":"Computational science","score":0.39965397119522095},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.223749041557312},{"id":"https://openalex.org/keywords/mathematics","display_name":"Mathematics","score":0.11577233672142029}],"concepts":[{"id":"https://openalex.org/C48044578","wikidata":"https://www.wikidata.org/wiki/Q727490","display_name":"Scalability","level":2,"score":0.8236683011054993},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.8133112192153931},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.7859236001968384},{"id":"https://openalex.org/C4822641","wikidata":"https://www.wikidata.org/wiki/Q846651","display_name":"Multiprocessing","level":2,"score":0.7345020771026611},{"id":"https://openalex.org/C2781172179","wikidata":"https://www.wikidata.org/wiki/Q853109","display_name":"Parallelism (grammar)","level":2,"score":0.7226472496986389},{"id":"https://openalex.org/C2778755073","wikidata":"https://www.wikidata.org/wiki/Q10858537","display_name":"Scale (ratio)","level":2,"score":0.5750285387039185},{"id":"https://openalex.org/C165696696","wikidata":"https://www.wikidata.org/wiki/Q11287","display_name":"Exploit","level":2,"score":0.5544626712799072},{"id":"https://openalex.org/C99844830","wikidata":"https://www.wikidata.org/wiki/Q102441924","display_name":"Scaling","level":2,"score":0.5389993190765381},{"id":"https://openalex.org/C45374587","wikidata":"https://www.wikidata.org/wiki/Q12525525","display_name":"Computation","level":2,"score":0.5376698970794678},{"id":"https://openalex.org/C28719098","wikidata":"https://www.wikidata.org/wiki/Q44946","display_name":"Point (geometry)","level":2,"score":0.5211641788482666},{"id":"https://openalex.org/C139352143","wikidata":"https://www.wikidata.org/wiki/Q82571","display_name":"Linear algebra","level":2,"score":0.4608108699321747},{"id":"https://openalex.org/C155253501","wikidata":"https://www.wikidata.org/wiki/Q461992","display_name":"Interior point method","level":2,"score":0.46002310514450073},{"id":"https://openalex.org/C42992933","wikidata":"https://www.wikidata.org/wiki/Q691169","display_name":"Task parallelism","level":3,"score":0.4555962085723877},{"id":"https://openalex.org/C165005293","wikidata":"https://www.wikidata.org/wiki/Q1074500","display_name":"Chip","level":2,"score":0.4204564392566681},{"id":"https://openalex.org/C459310","wikidata":"https://www.wikidata.org/wiki/Q117801","display_name":"Computational science","level":1,"score":0.39965397119522095},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.223749041557312},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.11577233672142029},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.0},{"id":"https://openalex.org/C2524010","wikidata":"https://www.wikidata.org/wiki/Q8087","display_name":"Geometry","level":1,"score":0.0},{"id":"https://openalex.org/C121332964","wikidata":"https://www.wikidata.org/wiki/Q413","display_name":"Physics","level":0,"score":0.0},{"id":"https://openalex.org/C62520636","wikidata":"https://www.wikidata.org/wiki/Q944","display_name":"Quantum mechanics","level":1,"score":0.0},{"id":"https://openalex.org/C38652104","wikidata":"https://www.wikidata.org/wiki/Q3510521","display_name":"Computer security","level":1,"score":0.0},{"id":"https://openalex.org/C77088390","wikidata":"https://www.wikidata.org/wiki/Q8513","display_name":"Database","level":1,"score":0.0}],"mesh":[],"locations_count":2,"locations":[{"id":"doi:10.1145/1362622.1362652","is_oa":false,"landing_page_url":"https://doi.org/10.1145/1362622.1362652","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 2007 ACM/IEEE conference on Supercomputing","raw_type":"proceedings-article"},{"id":"pmh:oai:CiteSeerX.psu:10.1.1.128.9050","is_oa":false,"landing_page_url":"http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.128.9050","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"http://sc07.supercomputing.org/schedule/pdf/pap432.pdf","raw_type":"text"}],"best_oa_location":null,"sustainable_development_goals":[{"id":"https://metadata.un.org/sdg/9","display_name":"Industry, innovation and infrastructure","score":0.550000011920929}],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":24,"referenced_works":["https://openalex.org/W219701461","https://openalex.org/W1481131999","https://openalex.org/W1555673550","https://openalex.org/W1556969930","https://openalex.org/W1728348608","https://openalex.org/W1991630019","https://openalex.org/W2012464173","https://openalex.org/W2022740893","https://openalex.org/W2037743346","https://openalex.org/W2044265095","https://openalex.org/W2046332585","https://openalex.org/W2051679444","https://openalex.org/W2070299075","https://openalex.org/W2100843445","https://openalex.org/W2103354892","https://openalex.org/W2107194324","https://openalex.org/W2111642243","https://openalex.org/W2139559439","https://openalex.org/W2141331848","https://openalex.org/W2142822378","https://openalex.org/W2170546376","https://openalex.org/W3029645440","https://openalex.org/W3104001151","https://openalex.org/W4301014524"],"related_works":["https://openalex.org/W2950520577","https://openalex.org/W2268046897","https://openalex.org/W74409296","https://openalex.org/W2003935582","https://openalex.org/W1554644772","https://openalex.org/W305742777","https://openalex.org/W2940653809","https://openalex.org/W2567390125","https://openalex.org/W2124295435","https://openalex.org/W2121547511"],"abstract_inverted_index":{"In":[0],"this":[1],"paper":[2],"we":[3],"describe":[4],"parallelization":[5],"of":[6,33,41,54,61,88],"interior-point":[7],"method":[8],"(IPM)":[9],"aimed":[10],"at":[11],"achieving":[12],"high":[13],"scalability":[14,87],"on":[15,90],"large-scale":[16],"chip-multiprocessors":[17],"(CMPs).":[18],"IPM":[19,38],"is":[20],"an":[21],"important":[22],"computational":[23],"technique":[24],"used":[25],"to":[26,74,92],"solve":[27],"optimization":[28,69],"problems":[29,70],"in":[30,45,67],"many":[31,68],"areas":[32],"science,":[34],"engineering":[35],"and":[36],"finance.":[37],"spends":[39],"most":[40,79],"its":[42],"computation":[43],"time":[44],"a":[46,58,77,84],"few":[47],"sparse":[48,63],"linear":[49],"algebra":[50],"kernels.":[51],"While":[52],"each":[53],"these":[55],"kernels":[56],"contains":[57],"large":[59,93],"amount":[60],"parallelism,":[62],"irregular":[64],"datasets":[65],"seen":[66],"make":[71],"parallelism":[72],"difficult":[73],"exploit.":[75],"As":[76],"result,":[78],"researchers":[80],"have":[81],"shown":[82],"only":[83],"relatively":[85],"low":[86],"4X-12X":[89],"medium":[91],"scale":[94],"parallel":[95],"machines.":[96]},"counts_by_year":[{"year":2016,"cited_by_count":1},{"year":2012,"cited_by_count":2}],"updated_date":"2026-04-05T17:49:38.594831","created_date":"2025-10-10T00:00:00"}