{"id":"https://openalex.org/W2071682149","doi":"https://doi.org/10.1145/1353610.1353625","title":"Sidewinder","display_name":"Sidewinder","publication_year":2008,"publication_date":"2008-04-05","ids":{"openalex":"https://openalex.org/W2071682149","doi":"https://doi.org/10.1145/1353610.1353625","mag":"2071682149"},"language":"en","primary_location":{"id":"doi:10.1145/1353610.1353625","is_oa":false,"landing_page_url":"https://doi.org/10.1145/1353610.1353625","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 2008 international workshop on System level interconnect prediction","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5081724582","display_name":"Jin Hu","orcid":"https://orcid.org/0000-0002-7563-4716"},"institutions":[{"id":"https://openalex.org/I27837315","display_name":"University of Michigan\u2013Ann Arbor","ror":"https://ror.org/00jmfr291","country_code":"US","type":"education","lineage":["https://openalex.org/I27837315"]}],"countries":["US"],"is_corresponding":true,"raw_author_name":"Jin Hu","raw_affiliation_strings":["University of Michigan, Ann Arbor, MI"],"affiliations":[{"raw_affiliation_string":"University of Michigan, Ann Arbor, MI","institution_ids":["https://openalex.org/I27837315"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5110108098","display_name":"Jarrod A. Roy","orcid":null},"institutions":[{"id":"https://openalex.org/I27837315","display_name":"University of Michigan\u2013Ann Arbor","ror":"https://ror.org/00jmfr291","country_code":"US","type":"education","lineage":["https://openalex.org/I27837315"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Jarrod A. Roy","raw_affiliation_strings":["University of Michigan, Ann Arbor, MI"],"affiliations":[{"raw_affiliation_string":"University of Michigan, Ann Arbor, MI","institution_ids":["https://openalex.org/I27837315"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5065370018","display_name":"Igor L. Markov","orcid":"https://orcid.org/0000-0002-3826-527X"},"institutions":[{"id":"https://openalex.org/I27837315","display_name":"University of Michigan\u2013Ann Arbor","ror":"https://ror.org/00jmfr291","country_code":"US","type":"education","lineage":["https://openalex.org/I27837315"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Igor L. Markov","raw_affiliation_strings":["University of Michigan, Ann Arbor, MI"],"affiliations":[{"raw_affiliation_string":"University of Michigan, Ann Arbor, MI","institution_ids":["https://openalex.org/I27837315"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":3,"corresponding_author_ids":["https://openalex.org/A5081724582"],"corresponding_institution_ids":["https://openalex.org/I27837315"],"apc_list":null,"apc_paid":null,"fwci":2.7052,"has_fulltext":false,"cited_by_count":31,"citation_normalized_percentile":{"value":0.89907307,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":99},"biblio":{"volume":null,"issue":null,"first_page":"73","last_page":"80"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9997000098228455,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9944000244140625,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7330129146575928},{"id":"https://openalex.org/keywords/scalability","display_name":"Scalability","score":0.7296396493911743},{"id":"https://openalex.org/keywords/routing","display_name":"Routing (electronic design automation)","score":0.7131296992301941},{"id":"https://openalex.org/keywords/router","display_name":"Router","score":0.6836264133453369},{"id":"https://openalex.org/keywords/network-routing","display_name":"Network routing","score":0.6244049072265625},{"id":"https://openalex.org/keywords/component","display_name":"Component (thermodynamics)","score":0.5024991035461426},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.4887568950653076},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.4746095538139343},{"id":"https://openalex.org/keywords/integer-programming","display_name":"Integer programming","score":0.4746093153953552},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.3009485900402069},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.258469820022583},{"id":"https://openalex.org/keywords/computer-network","display_name":"Computer network","score":0.22333970665931702}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7330129146575928},{"id":"https://openalex.org/C48044578","wikidata":"https://www.wikidata.org/wiki/Q727490","display_name":"Scalability","level":2,"score":0.7296396493911743},{"id":"https://openalex.org/C74172769","wikidata":"https://www.wikidata.org/wiki/Q1446839","display_name":"Routing (electronic design automation)","level":2,"score":0.7131296992301941},{"id":"https://openalex.org/C2775896111","wikidata":"https://www.wikidata.org/wiki/Q642560","display_name":"Router","level":2,"score":0.6836264133453369},{"id":"https://openalex.org/C2983435990","wikidata":"https://www.wikidata.org/wiki/Q22725","display_name":"Network routing","level":3,"score":0.6244049072265625},{"id":"https://openalex.org/C168167062","wikidata":"https://www.wikidata.org/wiki/Q1117970","display_name":"Component (thermodynamics)","level":2,"score":0.5024991035461426},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.4887568950653076},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.4746095538139343},{"id":"https://openalex.org/C56086750","wikidata":"https://www.wikidata.org/wiki/Q6042592","display_name":"Integer programming","level":2,"score":0.4746093153953552},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.3009485900402069},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.258469820022583},{"id":"https://openalex.org/C31258907","wikidata":"https://www.wikidata.org/wiki/Q1301371","display_name":"Computer network","level":1,"score":0.22333970665931702},{"id":"https://openalex.org/C77088390","wikidata":"https://www.wikidata.org/wiki/Q8513","display_name":"Database","level":1,"score":0.0},{"id":"https://openalex.org/C97355855","wikidata":"https://www.wikidata.org/wiki/Q11473","display_name":"Thermodynamics","level":1,"score":0.0},{"id":"https://openalex.org/C121332964","wikidata":"https://www.wikidata.org/wiki/Q413","display_name":"Physics","level":0,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1145/1353610.1353625","is_oa":false,"landing_page_url":"https://doi.org/10.1145/1353610.1353625","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 2008 international workshop on System level interconnect prediction","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"display_name":"Industry, innovation and infrastructure","id":"https://metadata.un.org/sdg/9","score":0.49000000953674316}],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":21,"referenced_works":["https://openalex.org/W1972047514","https://openalex.org/W1979569488","https://openalex.org/W1989970914","https://openalex.org/W2002886574","https://openalex.org/W2016999260","https://openalex.org/W2066356146","https://openalex.org/W2085073472","https://openalex.org/W2110827694","https://openalex.org/W2126446661","https://openalex.org/W2128161498","https://openalex.org/W2135477945","https://openalex.org/W2137890965","https://openalex.org/W2155462145","https://openalex.org/W2165545669","https://openalex.org/W2171122650","https://openalex.org/W2401610261","https://openalex.org/W2998050925","https://openalex.org/W3004540582","https://openalex.org/W3145128584","https://openalex.org/W4246219036","https://openalex.org/W4285719527"],"related_works":["https://openalex.org/W2110265185","https://openalex.org/W3146360095","https://openalex.org/W2127180614","https://openalex.org/W4235531327","https://openalex.org/W1603115038","https://openalex.org/W1964344619","https://openalex.org/W4245571887","https://openalex.org/W2040311870","https://openalex.org/W2177095534","https://openalex.org/W2132489107"],"abstract_inverted_index":{"We":[0],"propose":[1],"Sidewinder,":[2],"a":[3,15,43,82],"new":[4],"global":[5],"router":[6],"that":[7],"combines":[8],"pattern":[9],"routing":[10,13,131],"and":[11,49,86,95,105,117,146],"maze":[12],"in":[14,45,68,73],"novel,":[16],"incremental,":[17],"ILP":[18,51,78],"formulation.":[19],"It":[20],"is":[21,54,127],"the":[22,87],"first":[23],"flat":[24],"ILP-based":[25,114],"approach":[26],"scalable":[27],"enough":[28],"to":[29,91,113,120,129],"consider":[30],"over":[31,110],"104":[32],"GCells":[33],"at":[34,57],"once.":[35],"Moreover,":[36],"it":[37,139],"also":[38],"can":[39,65,140],"be":[40],"used":[41],"as":[42,134,136],"component":[44],"previously":[46],"proposed":[47],"multi-level":[48],"progressive":[50],"schemes.":[52],"Sidewinder":[53,101],"particularly":[55],"good":[56],"finding":[58],"routes":[59,90],"with":[60],"minimal":[61],"via":[62,107],"count,":[63],"which":[64],"improve":[66,96],"yield":[67],"sub-90nm":[69],"technologies.":[70],"Other":[71],"innovations":[72],"our":[74],"work":[75],"include":[76],"an":[77],"construction":[79],"based":[80],"on":[81],"dynamically-updated":[83],"congestion":[84,94],"map":[85],"use":[88],"ofC-shape":[89],"alleviate":[92],"local":[93],"routability.":[97],"On":[98],"well-known":[99],"benchmarks,":[100],"improves":[102],"routed":[103],"wirelength":[104],"reduces":[106],"count":[108],"by":[109],"6%":[111],"compared":[112,119],"BoxRouter":[115],"1.0":[116],"35.8%":[118],"DLM-based":[121],"FGR":[122],"1.0.":[123],"This":[124],"easy-to-implement":[125],"methodology":[126],"extensible":[128],"detail":[130],"of":[132],"ASICs":[133],"well":[135],"FPGAs":[137],"where":[138],"account":[141],"for":[142],"complex":[143],"design":[144],"rules":[145],"models.":[147]},"counts_by_year":[{"year":2026,"cited_by_count":1},{"year":2025,"cited_by_count":2},{"year":2024,"cited_by_count":5},{"year":2023,"cited_by_count":2},{"year":2022,"cited_by_count":3},{"year":2020,"cited_by_count":1},{"year":2018,"cited_by_count":1},{"year":2015,"cited_by_count":5},{"year":2013,"cited_by_count":2},{"year":2012,"cited_by_count":1}],"updated_date":"2026-03-12T08:34:05.389933","created_date":"2016-06-24T00:00:00"}
