{"id":"https://openalex.org/W2067564516","doi":"https://doi.org/10.1145/1353610.1353622","title":"Circuit and physical design of the MDGRAPE-4 on-chip network links","display_name":"Circuit and physical design of the MDGRAPE-4 on-chip network links","publication_year":2008,"publication_date":"2008-04-05","ids":{"openalex":"https://openalex.org/W2067564516","doi":"https://doi.org/10.1145/1353610.1353622","mag":"2067564516"},"language":"en","primary_location":{"id":"doi:10.1145/1353610.1353622","is_oa":false,"landing_page_url":"https://doi.org/10.1145/1353610.1353622","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 2008 international workshop on System level interconnect prediction","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5055388636","display_name":"Duraid Madina","orcid":null},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"Duraid Madina","raw_affiliation_strings":["Tokyo University, Meguro, Japan"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Tokyo University, Meguro, Japan","institution_ids":[]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5033083222","display_name":"Makoto Taiji","orcid":"https://orcid.org/0000-0002-5317-0500"},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"Makoto Taiji","raw_affiliation_strings":["RIKEN, Tsurumi, Japan"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"RIKEN, Tsurumi, Japan","institution_ids":[]}]}],"institutions":[],"countries_distinct_count":0,"institutions_distinct_count":2,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":1,"citation_normalized_percentile":{"value":0.12098285,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":90,"max":94},"biblio":{"volume":null,"issue":null,"first_page":"59","last_page":"64"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.9997000098228455,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.9997000098228455,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9990000128746033,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11417","display_name":"Advancements in PLL and VCO Technologies","score":0.9958000183105469,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/physical-design","display_name":"Physical design","score":0.6863189339637756},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.6760585308074951},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.5825854539871216},{"id":"https://openalex.org/keywords/chip","display_name":"Chip","score":0.5132960677146912},{"id":"https://openalex.org/keywords/key","display_name":"Key (lock)","score":0.49701932072639465},{"id":"https://openalex.org/keywords/electronic-circuit","display_name":"Electronic circuit","score":0.4712931215763092},{"id":"https://openalex.org/keywords/integrated-circuit-design","display_name":"Integrated circuit design","score":0.4548698961734772},{"id":"https://openalex.org/keywords/circuit-design","display_name":"Circuit design","score":0.45131564140319824},{"id":"https://openalex.org/keywords/quadrature","display_name":"Quadrature (astronomy)","score":0.42832309007644653},{"id":"https://openalex.org/keywords/differential-amplifier","display_name":"Differential amplifier","score":0.42718786001205444},{"id":"https://openalex.org/keywords/differential","display_name":"Differential (mechanical device)","score":0.4213881194591522},{"id":"https://openalex.org/keywords/amplifier","display_name":"Amplifier","score":0.4072369337081909},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.344571590423584},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.27366387844085693},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.24151611328125},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.20745497941970825},{"id":"https://openalex.org/keywords/telecommunications","display_name":"Telecommunications","score":0.16531512141227722},{"id":"https://openalex.org/keywords/bandwidth","display_name":"Bandwidth (computing)","score":0.1580583155155182}],"concepts":[{"id":"https://openalex.org/C188817802","wikidata":"https://www.wikidata.org/wiki/Q13426855","display_name":"Physical design","level":3,"score":0.6863189339637756},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6760585308074951},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.5825854539871216},{"id":"https://openalex.org/C165005293","wikidata":"https://www.wikidata.org/wiki/Q1074500","display_name":"Chip","level":2,"score":0.5132960677146912},{"id":"https://openalex.org/C26517878","wikidata":"https://www.wikidata.org/wiki/Q228039","display_name":"Key (lock)","level":2,"score":0.49701932072639465},{"id":"https://openalex.org/C134146338","wikidata":"https://www.wikidata.org/wiki/Q1815901","display_name":"Electronic circuit","level":2,"score":0.4712931215763092},{"id":"https://openalex.org/C74524168","wikidata":"https://www.wikidata.org/wiki/Q1074539","display_name":"Integrated circuit design","level":2,"score":0.4548698961734772},{"id":"https://openalex.org/C190560348","wikidata":"https://www.wikidata.org/wiki/Q3245116","display_name":"Circuit design","level":2,"score":0.45131564140319824},{"id":"https://openalex.org/C62869609","wikidata":"https://www.wikidata.org/wiki/Q28137","display_name":"Quadrature (astronomy)","level":2,"score":0.42832309007644653},{"id":"https://openalex.org/C11722477","wikidata":"https://www.wikidata.org/wiki/Q1056298","display_name":"Differential amplifier","level":4,"score":0.42718786001205444},{"id":"https://openalex.org/C93226319","wikidata":"https://www.wikidata.org/wiki/Q193137","display_name":"Differential (mechanical device)","level":2,"score":0.4213881194591522},{"id":"https://openalex.org/C194257627","wikidata":"https://www.wikidata.org/wiki/Q211554","display_name":"Amplifier","level":3,"score":0.4072369337081909},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.344571590423584},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.27366387844085693},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.24151611328125},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.20745497941970825},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.16531512141227722},{"id":"https://openalex.org/C2776257435","wikidata":"https://www.wikidata.org/wiki/Q1576430","display_name":"Bandwidth (computing)","level":2,"score":0.1580583155155182},{"id":"https://openalex.org/C38652104","wikidata":"https://www.wikidata.org/wiki/Q3510521","display_name":"Computer security","level":1,"score":0.0},{"id":"https://openalex.org/C146978453","wikidata":"https://www.wikidata.org/wiki/Q3798668","display_name":"Aerospace engineering","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1145/1353610.1353622","is_oa":false,"landing_page_url":"https://doi.org/10.1145/1353610.1353622","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 2008 international workshop on System level interconnect prediction","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"display_name":"Affordable and clean energy","score":0.6800000071525574,"id":"https://metadata.un.org/sdg/7"}],"awards":[],"funders":[{"id":"https://openalex.org/F4320334764","display_name":"Japan Society for the Promotion of Science","ror":"https://ror.org/00hhkn466"}],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":11,"referenced_works":["https://openalex.org/W1511351334","https://openalex.org/W1524885163","https://openalex.org/W1709147564","https://openalex.org/W2016778694","https://openalex.org/W2059193309","https://openalex.org/W2123871098","https://openalex.org/W2129267471","https://openalex.org/W2148808647","https://openalex.org/W2163411840","https://openalex.org/W2170155933","https://openalex.org/W2177001705"],"related_works":["https://openalex.org/W4389672975","https://openalex.org/W1965232212","https://openalex.org/W2109207559","https://openalex.org/W1987513258","https://openalex.org/W1963851171","https://openalex.org/W2134664711","https://openalex.org/W1974416117","https://openalex.org/W2159651504","https://openalex.org/W2168458994","https://openalex.org/W2086919462"],"abstract_inverted_index":{"We":[0,29],"present":[1,30],"the":[2,10,21,52],"novel":[3,47],"circuits":[4],"and":[5,36],"physical":[6],"design":[7],"methodology":[8],"of":[9,23,75],"MDGRAPE-4":[11,53],"NoC":[12],"links.":[13],"A":[14],"key":[15],"feature":[16],"enabling":[17],"efficient":[18],"operation":[19],"is":[20],"use":[22],"one-hot,":[24],"four":[25],"wire":[26],"(quadrature)":[27],"signalling.":[28],"our":[31],"quadrature":[32],"sense":[33],"amplifier":[34],"circuit,":[35],"compare":[37],"its":[38],"performance":[39],"to":[40,49,57],"standard":[41],"differential":[42],"designs.":[43],"Together":[44],"with":[45,71],"a":[46,62],"approach":[48],"link":[50],"layout,":[51],"links":[54,70],"are":[55],"designed":[56],"operate":[58],"at":[59],"8GHz":[60],"in":[61],"1.0V":[63],"65nm":[64],"process,":[65],"transporting":[66],"data":[67],"across":[68],"4.5mm":[69],"an":[72],"effective":[73],"cost":[74],"60fJ/b.":[76]},"counts_by_year":[{"year":2012,"cited_by_count":1}],"updated_date":"2026-06-11T09:08:48.828518","created_date":"2025-10-10T00:00:00"}