{"id":"https://openalex.org/W2138195591","doi":"https://doi.org/10.1145/1353610.1353612","title":"Interconnection lengths and delays estimation for communication links in FPGAs","display_name":"Interconnection lengths and delays estimation for communication links in FPGAs","publication_year":2008,"publication_date":"2008-04-05","ids":{"openalex":"https://openalex.org/W2138195591","doi":"https://doi.org/10.1145/1353610.1353612","mag":"2138195591"},"language":"en","primary_location":{"id":"doi:10.1145/1353610.1353612","is_oa":false,"landing_page_url":"https://doi.org/10.1145/1353610.1353612","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 2008 international workshop on System level interconnect prediction","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5103281227","display_name":"Terrence Mak","orcid":"https://orcid.org/0000-0003-1945-8292"},"institutions":[{"id":"https://openalex.org/I47508984","display_name":"Imperial College London","ror":"https://ror.org/041kmwe10","country_code":"GB","type":"education","lineage":["https://openalex.org/I47508984"]}],"countries":["GB"],"is_corresponding":true,"raw_author_name":"Terrence Mak","raw_affiliation_strings":["Imperial College, London, United Kngdm","Imperial College, London, United Kngdm#TAB#"],"affiliations":[{"raw_affiliation_string":"Imperial College, London, United Kngdm","institution_ids":["https://openalex.org/I47508984"]},{"raw_affiliation_string":"Imperial College, London, United Kngdm#TAB#","institution_ids":["https://openalex.org/I47508984"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5048050040","display_name":"Pete Sedcole","orcid":null},"institutions":[{"id":"https://openalex.org/I47508984","display_name":"Imperial College London","ror":"https://ror.org/041kmwe10","country_code":"GB","type":"education","lineage":["https://openalex.org/I47508984"]}],"countries":["GB"],"is_corresponding":false,"raw_author_name":"Pete Sedcole","raw_affiliation_strings":["Imperial College, London, United Kngdm","Imperial College, London, United Kngdm#TAB#"],"affiliations":[{"raw_affiliation_string":"Imperial College, London, United Kngdm","institution_ids":["https://openalex.org/I47508984"]},{"raw_affiliation_string":"Imperial College, London, United Kngdm#TAB#","institution_ids":["https://openalex.org/I47508984"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5091532722","display_name":"Peter Y. K. Cheung","orcid":"https://orcid.org/0000-0002-8236-1816"},"institutions":[{"id":"https://openalex.org/I47508984","display_name":"Imperial College London","ror":"https://ror.org/041kmwe10","country_code":"GB","type":"education","lineage":["https://openalex.org/I47508984"]}],"countries":["GB"],"is_corresponding":false,"raw_author_name":"Peter Y. K. Cheung","raw_affiliation_strings":["Imperial College, London, United Kngdm","Imperial College, London, United Kngdm#TAB#"],"affiliations":[{"raw_affiliation_string":"Imperial College, London, United Kngdm","institution_ids":["https://openalex.org/I47508984"]},{"raw_affiliation_string":"Imperial College, London, United Kngdm#TAB#","institution_ids":["https://openalex.org/I47508984"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5057940557","display_name":"Wayne Luk","orcid":"https://orcid.org/0000-0002-6750-927X"},"institutions":[{"id":"https://openalex.org/I47508984","display_name":"Imperial College London","ror":"https://ror.org/041kmwe10","country_code":"GB","type":"education","lineage":["https://openalex.org/I47508984"]}],"countries":["GB"],"is_corresponding":false,"raw_author_name":"Wayne Luk","raw_affiliation_strings":["Imperial College, London, United Kngdm","Imperial College, London, United Kngdm#TAB#"],"affiliations":[{"raw_affiliation_string":"Imperial College, London, United Kngdm","institution_ids":["https://openalex.org/I47508984"]},{"raw_affiliation_string":"Imperial College, London, United Kngdm#TAB#","institution_ids":["https://openalex.org/I47508984"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":4,"corresponding_author_ids":["https://openalex.org/A5103281227"],"corresponding_institution_ids":["https://openalex.org/I47508984"],"apc_list":null,"apc_paid":null,"fwci":2.1996,"has_fulltext":false,"cited_by_count":8,"citation_normalized_percentile":{"value":0.89337872,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":94},"biblio":{"volume":null,"issue":null,"first_page":"1","last_page":"10"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/interconnection","display_name":"Interconnection","score":0.8143201470375061},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.6999198198318481},{"id":"https://openalex.org/keywords/routing","display_name":"Routing (electronic design automation)","score":0.6947061419487},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.6719661951065063},{"id":"https://openalex.org/keywords/stochastic-modelling","display_name":"Stochastic modelling","score":0.45726853609085083},{"id":"https://openalex.org/keywords/variance","display_name":"Variance (accounting)","score":0.4556049406528473},{"id":"https://openalex.org/keywords/implementation","display_name":"Implementation","score":0.4470073878765106},{"id":"https://openalex.org/keywords/communications-system","display_name":"Communications system","score":0.42378056049346924},{"id":"https://openalex.org/keywords/computer-network","display_name":"Computer network","score":0.23956209421157837},{"id":"https://openalex.org/keywords/mathematics","display_name":"Mathematics","score":0.15174832940101624},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.12365838885307312}],"concepts":[{"id":"https://openalex.org/C123745756","wikidata":"https://www.wikidata.org/wiki/Q1665949","display_name":"Interconnection","level":2,"score":0.8143201470375061},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6999198198318481},{"id":"https://openalex.org/C74172769","wikidata":"https://www.wikidata.org/wiki/Q1446839","display_name":"Routing (electronic design automation)","level":2,"score":0.6947061419487},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.6719661951065063},{"id":"https://openalex.org/C127491075","wikidata":"https://www.wikidata.org/wiki/Q7617825","display_name":"Stochastic modelling","level":2,"score":0.45726853609085083},{"id":"https://openalex.org/C196083921","wikidata":"https://www.wikidata.org/wiki/Q7915758","display_name":"Variance (accounting)","level":2,"score":0.4556049406528473},{"id":"https://openalex.org/C26713055","wikidata":"https://www.wikidata.org/wiki/Q245962","display_name":"Implementation","level":2,"score":0.4470073878765106},{"id":"https://openalex.org/C101765175","wikidata":"https://www.wikidata.org/wiki/Q577764","display_name":"Communications system","level":2,"score":0.42378056049346924},{"id":"https://openalex.org/C31258907","wikidata":"https://www.wikidata.org/wiki/Q1301371","display_name":"Computer network","level":1,"score":0.23956209421157837},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.15174832940101624},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.12365838885307312},{"id":"https://openalex.org/C144133560","wikidata":"https://www.wikidata.org/wiki/Q4830453","display_name":"Business","level":0,"score":0.0},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.0},{"id":"https://openalex.org/C105795698","wikidata":"https://www.wikidata.org/wiki/Q12483","display_name":"Statistics","level":1,"score":0.0},{"id":"https://openalex.org/C121955636","wikidata":"https://www.wikidata.org/wiki/Q4116214","display_name":"Accounting","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1145/1353610.1353612","is_oa":false,"landing_page_url":"https://doi.org/10.1145/1353610.1353612","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 2008 international workshop on System level interconnect prediction","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"id":"https://metadata.un.org/sdg/9","score":0.4000000059604645,"display_name":"Industry, innovation and infrastructure"}],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":13,"referenced_works":["https://openalex.org/W1523051745","https://openalex.org/W1590243758","https://openalex.org/W1943309769","https://openalex.org/W2013783098","https://openalex.org/W2017843246","https://openalex.org/W2029459574","https://openalex.org/W2103839010","https://openalex.org/W2110265185","https://openalex.org/W2111608568","https://openalex.org/W2170116489","https://openalex.org/W2322524800","https://openalex.org/W4300306656","https://openalex.org/W6680971561"],"related_works":["https://openalex.org/W2120447654","https://openalex.org/W2977179488","https://openalex.org/W2144453115","https://openalex.org/W2128223750","https://openalex.org/W4238532390","https://openalex.org/W2188872161","https://openalex.org/W2961779879","https://openalex.org/W797688974","https://openalex.org/W2002978035","https://openalex.org/W2209382646"],"abstract_inverted_index":{"This":[0],"paper":[1,121],"presents":[2],"a":[3,17,111,142],"new":[4],"stochastic":[5,18,67],"model":[6,68,86],"to":[7,99,135],"predictinterconnection":[8],"lengths":[9,52],"of":[10,26,51,60,73,79,90,113],"communication":[11,107,143],"links":[12,61],"in":[13,63,119,141],"FPGAs.":[14],"Based":[15],"on":[16,39],"inter-module":[19],"routing":[20,139],"model,":[21],"expected":[22],"length":[23,41,74],"and":[24,53,92,103,145],"variance":[25],"interconnections":[27,148],"have":[28],"been":[29],"rigorously":[30],"derived":[31],"and,":[32,149],"thus,":[33],"delay":[34,91],"can":[35,96],"be":[36,97],"computed":[37],"based":[38],"the":[40,94,136,152],"estimate.":[42],"The":[43,66,130],"theoretical":[44],"results":[45,50],"are":[46,56],"compared":[47],"with":[48,75],"experimental":[49],"delays,":[54],"which":[55,125],"obtained":[57],"from":[58],"implementations":[59],"circuits":[62],"an":[64,70,76,122],"FPGA.":[65],"provides":[69],"accurate":[71],"prediction":[72],"average":[77],"error":[78],"6.3%.":[80],"Results":[81],"also":[82,117],"show":[83],"that":[84],"theproposed":[85],"produces":[87],"reliable":[88],"predictions":[89],"therefore":[93],"methodology":[95],"applied":[98],"early":[100],"stage":[101],"planning":[102],"design":[104],"optimization":[105],"for":[106,138],"links.":[108],"Moreover,":[109],"as":[110],"byproduct":[112],"this":[114,120],"work,":[115],"we":[116,126],"present":[118],"interesting":[123],"phenomenon":[124],"term":[127],"\"interconnection":[128],"fringing\".":[129],"fringing":[131],"effect":[132],"is":[133],"attributed":[134],"competition":[137],"resources":[140],"link":[144],"will":[146],"lengthen":[147],"therefore,":[150],"increase":[151],"delay.":[153]},"counts_by_year":[{"year":2014,"cited_by_count":1},{"year":2013,"cited_by_count":1}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}