{"id":"https://openalex.org/W2085612442","doi":"https://doi.org/10.1145/1344671.1344717","title":"When FPGAs are better at floating-point than microprocessors","display_name":"When FPGAs are better at floating-point than microprocessors","publication_year":2008,"publication_date":"2008-02-24","ids":{"openalex":"https://openalex.org/W2085612442","doi":"https://doi.org/10.1145/1344671.1344717","mag":"2085612442"},"language":"en","primary_location":{"id":"doi:10.1145/1344671.1344717","is_oa":false,"landing_page_url":"https://doi.org/10.1145/1344671.1344717","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 16th international ACM/SIGDA symposium on Field programmable gate arrays","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":true,"oa_status":"green","oa_url":"https://ens-lyon.hal.science/ensl-00174627","any_repository_has_fulltext":true},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5035966925","display_name":"Florent de Dinechin","orcid":"https://orcid.org/0000-0003-4927-3301"},"institutions":[{"id":"https://openalex.org/I100532134","display_name":"Universit\u00e9 Claude Bernard Lyon 1","ror":"https://ror.org/029brtt94","country_code":"FR","type":"education","lineage":["https://openalex.org/I100532134","https://openalex.org/I203339264"]},{"id":"https://openalex.org/I113428412","display_name":"\u00c9cole Normale Sup\u00e9rieure de Lyon","ror":"https://ror.org/04zmssz18","country_code":"FR","type":"education","lineage":["https://openalex.org/I113428412","https://openalex.org/I203339264"]}],"countries":["FR"],"is_corresponding":false,"raw_author_name":"Florent de Dinechin","raw_affiliation_strings":["\u00c9cole Normale Sup\u00e9rieure de Lyon/Universit\u00e9 de Lyon, Lyon, France"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"\u00c9cole Normale Sup\u00e9rieure de Lyon/Universit\u00e9 de Lyon, Lyon, France","institution_ids":["https://openalex.org/I113428412","https://openalex.org/I100532134"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5015632143","display_name":"J\u00e9r\u00e9mie Detrey","orcid":"https://orcid.org/0000-0001-5198-858X"},"institutions":[{"id":"https://openalex.org/I100532134","display_name":"Universit\u00e9 Claude Bernard Lyon 1","ror":"https://ror.org/029brtt94","country_code":"FR","type":"education","lineage":["https://openalex.org/I100532134","https://openalex.org/I203339264"]},{"id":"https://openalex.org/I113428412","display_name":"\u00c9cole Normale Sup\u00e9rieure de Lyon","ror":"https://ror.org/04zmssz18","country_code":"FR","type":"education","lineage":["https://openalex.org/I113428412","https://openalex.org/I203339264"]}],"countries":["FR"],"is_corresponding":false,"raw_author_name":"J\u00e9r\u00e9mie Detrey","raw_affiliation_strings":["\u00c9cole Normale Sup\u00e9rieure de Lyon/Universit\u00e9 de Lyon, Lyon, France"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"\u00c9cole Normale Sup\u00e9rieure de Lyon/Universit\u00e9 de Lyon, Lyon, France","institution_ids":["https://openalex.org/I113428412","https://openalex.org/I100532134"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5030846791","display_name":"Octavian Cre\u0163","orcid":"https://orcid.org/0000-0002-6657-634X"},"institutions":[{"id":"https://openalex.org/I158333966","display_name":"Technical University of Cluj-Napoca","ror":"https://ror.org/03r8nwp71","country_code":"RO","type":"education","lineage":["https://openalex.org/I158333966"]}],"countries":["RO"],"is_corresponding":false,"raw_author_name":"Octavian Cret","raw_affiliation_strings":["Technical University of Cluj-Napoca, Cluj-Napoca, Romania"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Technical University of Cluj-Napoca, Cluj-Napoca, Romania","institution_ids":["https://openalex.org/I158333966"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5051617831","display_name":"Radu Tudoran","orcid":null},"institutions":[{"id":"https://openalex.org/I158333966","display_name":"Technical University of Cluj-Napoca","ror":"https://ror.org/03r8nwp71","country_code":"RO","type":"education","lineage":["https://openalex.org/I158333966"]}],"countries":["RO"],"is_corresponding":false,"raw_author_name":"Radu Tudoran","raw_affiliation_strings":["Technical University of Cluj-Napoca, Cluj-Napoca, Romania"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Technical University of Cluj-Napoca, Cluj-Napoca, Romania","institution_ids":["https://openalex.org/I158333966"]}]}],"institutions":[],"countries_distinct_count":2,"institutions_distinct_count":4,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":7.0374,"has_fulltext":false,"cited_by_count":37,"citation_normalized_percentile":{"value":0.9707151,"is_in_top_1_percent":false,"is_in_top_10_percent":true},"cited_by_percentile_year":{"min":89,"max":98},"biblio":{"volume":null,"issue":null,"first_page":"260","last_page":"260"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11697","display_name":"Numerical Methods and Algorithms","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1703","display_name":"Computational Theory and Mathematics"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11697","display_name":"Numerical Methods and Algorithms","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1703","display_name":"Computational Theory and Mathematics"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9961000084877014,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11034","display_name":"Digital Filter Design and Implementation","score":0.9959999918937683,"subfield":{"id":"https://openalex.org/subfields/1711","display_name":"Signal Processing"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.8089579343795776},{"id":"https://openalex.org/keywords/floating-point","display_name":"Floating point","score":0.8008993864059448},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7746684551239014},{"id":"https://openalex.org/keywords/double-precision-floating-point-format","display_name":"Double-precision floating-point format","score":0.5199260115623474},{"id":"https://openalex.org/keywords/flexibility","display_name":"Flexibility (engineering)","score":0.5118545889854431},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.4985511302947998},{"id":"https://openalex.org/keywords/computation","display_name":"Computation","score":0.4895678460597992},{"id":"https://openalex.org/keywords/microprocessor","display_name":"Microprocessor","score":0.45581287145614624},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.43532779812812805},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.4018869996070862},{"id":"https://openalex.org/keywords/operating-system","display_name":"Operating system","score":0.13481280207633972},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.12633296847343445},{"id":"https://openalex.org/keywords/mathematics","display_name":"Mathematics","score":0.08790454268455505}],"concepts":[{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.8089579343795776},{"id":"https://openalex.org/C84211073","wikidata":"https://www.wikidata.org/wiki/Q117879","display_name":"Floating point","level":2,"score":0.8008993864059448},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7746684551239014},{"id":"https://openalex.org/C35912277","wikidata":"https://www.wikidata.org/wiki/Q1243369","display_name":"Double-precision floating-point format","level":3,"score":0.5199260115623474},{"id":"https://openalex.org/C2780598303","wikidata":"https://www.wikidata.org/wiki/Q65921492","display_name":"Flexibility (engineering)","level":2,"score":0.5118545889854431},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.4985511302947998},{"id":"https://openalex.org/C45374587","wikidata":"https://www.wikidata.org/wiki/Q12525525","display_name":"Computation","level":2,"score":0.4895678460597992},{"id":"https://openalex.org/C2780728072","wikidata":"https://www.wikidata.org/wiki/Q5297","display_name":"Microprocessor","level":2,"score":0.45581287145614624},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.43532779812812805},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.4018869996070862},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.13481280207633972},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.12633296847343445},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.08790454268455505},{"id":"https://openalex.org/C105795698","wikidata":"https://www.wikidata.org/wiki/Q12483","display_name":"Statistics","level":1,"score":0.0}],"mesh":[],"locations_count":5,"locations":[{"id":"doi:10.1145/1344671.1344717","is_oa":false,"landing_page_url":"https://doi.org/10.1145/1344671.1344717","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 16th international ACM/SIGDA symposium on Field programmable gate arrays","raw_type":"proceedings-article"},{"id":"pmh:oai:CiteSeerX.psu:10.1.1.542.8381","is_oa":false,"landing_page_url":"http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.542.8381","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"http://www.loria.fr/~detreyje/publications/DinDetCreTud_lip_2007.pdf","raw_type":"text"},{"id":"pmh:oai:CiteSeerX.psu:10.1.1.561.8971","is_oa":false,"landing_page_url":"http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.561.8971","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"http://hal-ens-lyon.archives-ouvertes.fr/docs/00/17/46/27/PDF/DinechinDetreyCret.pdf","raw_type":"text"},{"id":"pmh:oai:CiteSeerX.psu:10.1.1.929.2507","is_oa":false,"landing_page_url":"http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.929.2507","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"https://hal-ens-lyon.archives-ouvertes.fr/ensl-00174627/document/","raw_type":"text"},{"id":"pmh:oai:HAL:ensl-00174627v1","is_oa":true,"landing_page_url":"https://ens-lyon.hal.science/ensl-00174627","pdf_url":null,"source":{"id":"https://openalex.org/S4306402512","display_name":"HAL (Le Centre pour la Communication Scientifique Directe)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/I1294671590","host_organization_name":"Centre National de la Recherche Scientifique","host_organization_lineage":["https://openalex.org/I1294671590"],"host_organization_lineage_names":[],"type":"repository"},"license":"other-oa","license_id":"https://openalex.org/licenses/other-oa","version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"2007","raw_type":"Preprints, Working Papers, ..."}],"best_oa_location":{"id":"pmh:oai:HAL:ensl-00174627v1","is_oa":true,"landing_page_url":"https://ens-lyon.hal.science/ensl-00174627","pdf_url":null,"source":{"id":"https://openalex.org/S4306402512","display_name":"HAL (Le Centre pour la Communication Scientifique Directe)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/I1294671590","host_organization_name":"Centre National de la Recherche Scientifique","host_organization_lineage":["https://openalex.org/I1294671590"],"host_organization_lineage_names":[],"type":"repository"},"license":"other-oa","license_id":"https://openalex.org/licenses/other-oa","version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"2007","raw_type":"Preprints, Working Papers, ..."},"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":39,"referenced_works":["https://openalex.org/W134377716","https://openalex.org/W266318588","https://openalex.org/W1480333149","https://openalex.org/W1483383428","https://openalex.org/W1538368719","https://openalex.org/W1574449651","https://openalex.org/W1594496874","https://openalex.org/W1594843402","https://openalex.org/W1968165559","https://openalex.org/W1971988695","https://openalex.org/W1984670676","https://openalex.org/W1991973578","https://openalex.org/W1995574761","https://openalex.org/W2020804487","https://openalex.org/W2061624656","https://openalex.org/W2096417134","https://openalex.org/W2102862134","https://openalex.org/W2105158708","https://openalex.org/W2109591842","https://openalex.org/W2110704067","https://openalex.org/W2120978237","https://openalex.org/W2126069080","https://openalex.org/W2126380220","https://openalex.org/W2132730902","https://openalex.org/W2146981186","https://openalex.org/W2152567198","https://openalex.org/W2158793378","https://openalex.org/W2160001263","https://openalex.org/W2161439686","https://openalex.org/W2161513497","https://openalex.org/W2162487360","https://openalex.org/W2162585354","https://openalex.org/W2165875079","https://openalex.org/W2167110608","https://openalex.org/W2169004268","https://openalex.org/W2171404670","https://openalex.org/W2568063366","https://openalex.org/W2752853835","https://openalex.org/W3021014091"],"related_works":["https://openalex.org/W3215589575","https://openalex.org/W3150959508","https://openalex.org/W4297795876","https://openalex.org/W1571090276","https://openalex.org/W2012407419","https://openalex.org/W2773283032","https://openalex.org/W2336476964","https://openalex.org/W2239119680","https://openalex.org/W1973800584","https://openalex.org/W3150370983"],"abstract_inverted_index":{"It":[0],"has":[1],"been":[2],"shown":[3],"that":[4],"FPGAs":[5],"could":[6,131],"outperform":[7],"high-end":[8],"microprocessors":[9],"on":[10],"floating-point":[11,60,136,169],"computations":[12],"thanks":[13],"to":[14,134,165],"massive":[15],"parallelism.":[16],"However,":[17,138],"most":[18],"previous":[19],"studies":[20],"re-implement":[21],"in":[22,28,52,98],"the":[23,25,41,45,49,54,144,166],"FPGA":[24,55,129],"operators":[26,94],"present":[27],"a":[29,58,126],"processor.":[30],"This":[31],"conservative":[32],"approach":[33],"is":[34,156,158],"relatively":[35],"straightforward,":[36],"but":[37,67],"it":[38],"doesn't":[39],"exploit":[40],"greater":[42],"flexibility":[43],"of":[44,57,146,168],"FPGA.":[46],"We":[47],"survey":[48],"many":[50],"ways":[51],"which":[53],"implementation":[56,167],"given":[59],"computation":[61],"can":[62],"be":[63,132],"not":[64,142],"only":[65],"faster,":[66],"also":[68],"more":[69,162],"accurate":[70],"than":[71],"its":[72],"microprocessor":[73],"counterpart.":[74],"Techniques":[75],"studied":[76],"here":[77],"include":[78],"custom":[79],"precision,":[80],"mixing":[81],"and":[82,85,113,176],"matching":[83],"fixed-":[84],"floating-point,":[86],"specific":[87],"accumulator":[88],"design,":[89],"dedicated":[90],"architectures":[91],"for":[92],"coarser":[93],"implemented":[95],"as":[96,101,110,150,172],"software":[97],"processors":[99],"(such":[100],"elementary":[102],"functions":[103],"or":[104],"Euclidean":[105],"norms),":[106],"operator":[107],"specialization":[108],"such":[109,122,171],"constant":[111],"multiplication,":[112],"others.":[114],"The":[115],"FloPoCo":[116],"project":[117],"(http://www.ens-lyon.fr/LIP/Arenaire/Ware/FloPoCo/)":[118],"aims":[119],"at":[120],"providing":[121],"non-standard":[123],"operators.":[124],"As":[125],"conclusion,":[127],"current":[128],"fabrics":[130],"enhanced":[133],"improve":[135],"performance.":[137],"these":[139],"enhancements":[140],"should":[141],"take":[143],"form":[145],"hard":[147],"FPU":[148],"blocks":[149,161],"others":[151],"have":[152],"suggested.":[153],"Instead,":[154],"what":[155],"needed":[157],"smaller":[159],"building":[160],"generally":[163],"useful":[164],"operators,":[170],"cascadable":[173],"barrel":[174],"shifters":[175],"leading":[177],"zero":[178],"counters":[179]},"counts_by_year":[{"year":2021,"cited_by_count":2},{"year":2020,"cited_by_count":1},{"year":2019,"cited_by_count":1},{"year":2017,"cited_by_count":2},{"year":2016,"cited_by_count":2},{"year":2015,"cited_by_count":3},{"year":2014,"cited_by_count":2},{"year":2013,"cited_by_count":5},{"year":2012,"cited_by_count":2}],"updated_date":"2026-06-11T09:08:48.828518","created_date":"2025-10-10T00:00:00"}
