{"id":"https://openalex.org/W1981196695","doi":"https://doi.org/10.1145/1344671.1344713","title":"Measuring and modeling FPGA clock variability","display_name":"Measuring and modeling FPGA clock variability","publication_year":2008,"publication_date":"2008-02-24","ids":{"openalex":"https://openalex.org/W1981196695","doi":"https://doi.org/10.1145/1344671.1344713","mag":"1981196695"},"language":"en","primary_location":{"id":"doi:10.1145/1344671.1344713","is_oa":false,"landing_page_url":"https://doi.org/10.1145/1344671.1344713","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 16th international ACM/SIGDA symposium on Field programmable gate arrays","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5048050040","display_name":"Pete Sedcole","orcid":null},"institutions":[{"id":"https://openalex.org/I47508984","display_name":"Imperial College London","ror":"https://ror.org/041kmwe10","country_code":"GB","type":"education","lineage":["https://openalex.org/I47508984"]}],"countries":["GB"],"is_corresponding":true,"raw_author_name":"Pete Sedcole","raw_affiliation_strings":["Imperial College London, London, United Kingdom"],"affiliations":[{"raw_affiliation_string":"Imperial College London, London, United Kingdom","institution_ids":["https://openalex.org/I47508984"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5051758515","display_name":"Justin S. J. Wong","orcid":"https://orcid.org/0000-0002-4378-1199"},"institutions":[{"id":"https://openalex.org/I47508984","display_name":"Imperial College London","ror":"https://ror.org/041kmwe10","country_code":"GB","type":"education","lineage":["https://openalex.org/I47508984"]}],"countries":["GB"],"is_corresponding":false,"raw_author_name":"Justin S. Wong","raw_affiliation_strings":["Imperial College London, London, United Kingdom"],"affiliations":[{"raw_affiliation_string":"Imperial College London, London, United Kingdom","institution_ids":["https://openalex.org/I47508984"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5091532722","display_name":"Peter Y. K. Cheung","orcid":"https://orcid.org/0000-0002-8236-1816"},"institutions":[{"id":"https://openalex.org/I47508984","display_name":"Imperial College London","ror":"https://ror.org/041kmwe10","country_code":"GB","type":"education","lineage":["https://openalex.org/I47508984"]}],"countries":["GB"],"is_corresponding":false,"raw_author_name":"Peter Y.K. Cheung","raw_affiliation_strings":["Imperial College London, London, United Kingdom"],"affiliations":[{"raw_affiliation_string":"Imperial College London, London, United Kingdom","institution_ids":["https://openalex.org/I47508984"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":3,"corresponding_author_ids":["https://openalex.org/A5048050040"],"corresponding_institution_ids":["https://openalex.org/I47508984"],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":0,"citation_normalized_percentile":{"value":0.0588795,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":null,"issue":null,"first_page":"258","last_page":"258"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9995999932289124,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9995999932289124,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9995999932289124,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9995999932289124,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/clock-skew","display_name":"Clock skew","score":0.8414092063903809},{"id":"https://openalex.org/keywords/skew","display_name":"Skew","score":0.805728554725647},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.7813978791236877},{"id":"https://openalex.org/keywords/digital-clock-manager","display_name":"Digital clock manager","score":0.7136628031730652},{"id":"https://openalex.org/keywords/static-timing-analysis","display_name":"Static timing analysis","score":0.6343553066253662},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.6146937608718872},{"id":"https://openalex.org/keywords/clock-network","display_name":"Clock network","score":0.5674251914024353},{"id":"https://openalex.org/keywords/timing-failure","display_name":"Timing failure","score":0.535284161567688},{"id":"https://openalex.org/keywords/process-variation","display_name":"Process variation","score":0.4797614514827728},{"id":"https://openalex.org/keywords/clock-domain-crossing","display_name":"Clock domain crossing","score":0.46357396245002747},{"id":"https://openalex.org/keywords/process","display_name":"Process (computing)","score":0.45700135827064514},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.4425821602344513},{"id":"https://openalex.org/keywords/clock-signal","display_name":"Clock signal","score":0.4413056969642639},{"id":"https://openalex.org/keywords/path","display_name":"Path (computing)","score":0.43585532903671265},{"id":"https://openalex.org/keywords/electronic-circuit","display_name":"Electronic circuit","score":0.4277192950248718},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.26633548736572266},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.20364752411842346},{"id":"https://openalex.org/keywords/synchronous-circuit","display_name":"Synchronous circuit","score":0.15645736455917358},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.1100197434425354},{"id":"https://openalex.org/keywords/telecommunications","display_name":"Telecommunications","score":0.0947016179561615},{"id":"https://openalex.org/keywords/jitter","display_name":"Jitter","score":0.07807046175003052}],"concepts":[{"id":"https://openalex.org/C60501442","wikidata":"https://www.wikidata.org/wiki/Q4382014","display_name":"Clock skew","level":4,"score":0.8414092063903809},{"id":"https://openalex.org/C43711488","wikidata":"https://www.wikidata.org/wiki/Q7534783","display_name":"Skew","level":2,"score":0.805728554725647},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.7813978791236877},{"id":"https://openalex.org/C113074038","wikidata":"https://www.wikidata.org/wiki/Q5276052","display_name":"Digital clock manager","level":5,"score":0.7136628031730652},{"id":"https://openalex.org/C93682380","wikidata":"https://www.wikidata.org/wiki/Q2025226","display_name":"Static timing analysis","level":2,"score":0.6343553066253662},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6146937608718872},{"id":"https://openalex.org/C2778182565","wikidata":"https://www.wikidata.org/wiki/Q1752879","display_name":"Clock network","level":5,"score":0.5674251914024353},{"id":"https://openalex.org/C104654189","wikidata":"https://www.wikidata.org/wiki/Q7806740","display_name":"Timing failure","level":5,"score":0.535284161567688},{"id":"https://openalex.org/C93389723","wikidata":"https://www.wikidata.org/wiki/Q7247313","display_name":"Process variation","level":3,"score":0.4797614514827728},{"id":"https://openalex.org/C127204226","wikidata":"https://www.wikidata.org/wiki/Q5134799","display_name":"Clock domain crossing","level":5,"score":0.46357396245002747},{"id":"https://openalex.org/C98045186","wikidata":"https://www.wikidata.org/wiki/Q205663","display_name":"Process (computing)","level":2,"score":0.45700135827064514},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.4425821602344513},{"id":"https://openalex.org/C137059387","wikidata":"https://www.wikidata.org/wiki/Q426882","display_name":"Clock signal","level":3,"score":0.4413056969642639},{"id":"https://openalex.org/C2777735758","wikidata":"https://www.wikidata.org/wiki/Q817765","display_name":"Path (computing)","level":2,"score":0.43585532903671265},{"id":"https://openalex.org/C134146338","wikidata":"https://www.wikidata.org/wiki/Q1815901","display_name":"Electronic circuit","level":2,"score":0.4277192950248718},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.26633548736572266},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.20364752411842346},{"id":"https://openalex.org/C42196554","wikidata":"https://www.wikidata.org/wiki/Q1186179","display_name":"Synchronous circuit","level":4,"score":0.15645736455917358},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.1100197434425354},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.0947016179561615},{"id":"https://openalex.org/C134652429","wikidata":"https://www.wikidata.org/wiki/Q1052698","display_name":"Jitter","level":2,"score":0.07807046175003052},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.0},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1145/1344671.1344713","is_oa":false,"landing_page_url":"https://doi.org/10.1145/1344671.1344713","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 16th international ACM/SIGDA symposium on Field programmable gate arrays","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":0,"referenced_works":[],"related_works":["https://openalex.org/W2088914741","https://openalex.org/W4247180033","https://openalex.org/W2559451387","https://openalex.org/W1596690381","https://openalex.org/W2127892766","https://openalex.org/W2617666058","https://openalex.org/W4247089581","https://openalex.org/W2144282137","https://openalex.org/W1525888526","https://openalex.org/W2090213929"],"abstract_inverted_index":{"As":[0],"integrated":[1],"circuits":[2,55],"are":[3,30,33,61],"scaled":[4],"down":[5],"it":[6],"becomes":[7],"difficult":[8],"to":[9,94],"maintain":[10],"uniformity":[11],"in":[12,50,79,86],"process":[13],"parameters":[14],"across":[15],"each":[16],"individual":[17],"die.":[18],"To":[19],"avoid":[20],"significant":[21,74],"performance":[22,37,105],"loss":[23],"through":[24],"pessimistic":[25],"over-design":[26],"new":[27],"design":[28],"strategies":[29,96],"required":[31],"that":[32,67],"cognizant":[34],"of":[35,44,84,101,106],"within-die":[36],"variability.":[38],"This":[39],"paper":[40],"examines":[41],"the":[42,47,99,104],"effect":[43],"variability":[45,69,78],"on":[46,103],"clock":[48,58,88],"resources":[49],"FPGA":[51,87],"devices.":[52],"Techniques":[53],"and":[54,92],"for":[56,97],"measuring":[57],"skew":[59,68],"variations":[60,102],"presented,":[62],"with":[63],"initial":[64],"results":[65],"indicating":[66],"is":[70,90],"at":[71],"least":[72],"as":[73,75],"signal":[76],"path":[77],"modern":[80],"FPGAs.":[81],"A":[82],"model":[83],"variation":[85],"networks":[89],"proposed,":[91],"used":[93],"suggest":[95],"reducing":[98],"impact":[100],"implemented":[107],"designs":[108]},"counts_by_year":[],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}
