{"id":"https://openalex.org/W2123173853","doi":"https://doi.org/10.1145/1344671.1344683","title":"Lithographic aerial image simulation with FPGA-based hardwareacceleration","display_name":"Lithographic aerial image simulation with FPGA-based hardwareacceleration","publication_year":2008,"publication_date":"2008-02-24","ids":{"openalex":"https://openalex.org/W2123173853","doi":"https://doi.org/10.1145/1344671.1344683","mag":"2123173853"},"language":"en","primary_location":{"id":"doi:10.1145/1344671.1344683","is_oa":false,"landing_page_url":"https://doi.org/10.1145/1344671.1344683","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 16th international ACM/SIGDA symposium on Field programmable gate arrays","raw_type":"proceedings-article"},"type":"conference-paper","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5016776689","display_name":"Jason Cong","orcid":"https://orcid.org/0000-0003-2887-6963"},"institutions":[{"id":"https://openalex.org/I161318765","display_name":"University of California, Los Angeles","ror":"https://ror.org/046rm7j60","country_code":"US","type":"education","lineage":["https://openalex.org/I161318765"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Jason Cong","raw_affiliation_strings":["University of California: Los Angeles, Los Angeles, CA",", University of California Los Angeles, Los Angeles, CA#TAB#"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"University of California: Los Angeles, Los Angeles, CA","institution_ids":["https://openalex.org/I161318765"]},{"raw_affiliation_string":", University of California Los Angeles, Los Angeles, CA#TAB#","institution_ids":["https://openalex.org/I161318765"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5100458990","display_name":"Yi Zou","orcid":"https://orcid.org/0000-0002-4382-4670"},"institutions":[{"id":"https://openalex.org/I161318765","display_name":"University of California, Los Angeles","ror":"https://ror.org/046rm7j60","country_code":"US","type":"education","lineage":["https://openalex.org/I161318765"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Yi Zou","raw_affiliation_strings":["University of California: Los Angeles, Los Angeles, CA",", University of California Los Angeles, Los Angeles, CA#TAB#"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"University of California: Los Angeles, Los Angeles, CA","institution_ids":["https://openalex.org/I161318765"]},{"raw_affiliation_string":", University of California Los Angeles, Los Angeles, CA#TAB#","institution_ids":["https://openalex.org/I161318765"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":1,"corresponding_author_ids":[],"corresponding_institution_ids":["https://openalex.org/I161318765"],"apc_list":null,"apc_paid":null,"fwci":6.642,"has_fulltext":false,"cited_by_count":21,"citation_normalized_percentile":{"value":0.97758584,"is_in_top_1_percent":false,"is_in_top_10_percent":true},"cited_by_percentile_year":{"min":90,"max":97},"biblio":{"volume":null,"issue":null,"first_page":"67","last_page":"76"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11338","display_name":"Advancements in Photolithography Techniques","score":0.9991000294685364,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11338","display_name":"Advancements in Photolithography Techniques","score":0.9991000294685364,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9975000023841858,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9939000010490417,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/speedup","display_name":"Speedup","score":0.8261826038360596},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.8075283765792847},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.6733651161193848},{"id":"https://openalex.org/keywords/design-for-manufacturability","display_name":"Design for manufacturability","score":0.6678368449211121},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.5015442371368408},{"id":"https://openalex.org/keywords/block","display_name":"Block (permutation group theory)","score":0.4869178533554077},{"id":"https://openalex.org/keywords/microprocessor","display_name":"Microprocessor","score":0.4695105254650116},{"id":"https://openalex.org/keywords/hardware-acceleration","display_name":"Hardware acceleration","score":0.44193384051322937},{"id":"https://openalex.org/keywords/microblaze","display_name":"MicroBlaze","score":0.44072476029396057},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.43329474329948425},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.37056633830070496}],"concepts":[{"id":"https://openalex.org/C68339613","wikidata":"https://www.wikidata.org/wiki/Q1549489","display_name":"Speedup","level":2,"score":0.8261826038360596},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.8075283765792847},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.6733651161193848},{"id":"https://openalex.org/C62064638","wikidata":"https://www.wikidata.org/wiki/Q553878","display_name":"Design for manufacturability","level":2,"score":0.6678368449211121},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.5015442371368408},{"id":"https://openalex.org/C2777210771","wikidata":"https://www.wikidata.org/wiki/Q4927124","display_name":"Block (permutation group theory)","level":2,"score":0.4869178533554077},{"id":"https://openalex.org/C2780728072","wikidata":"https://www.wikidata.org/wiki/Q5297","display_name":"Microprocessor","level":2,"score":0.4695105254650116},{"id":"https://openalex.org/C13164978","wikidata":"https://www.wikidata.org/wiki/Q600158","display_name":"Hardware acceleration","level":3,"score":0.44193384051322937},{"id":"https://openalex.org/C2777575374","wikidata":"https://www.wikidata.org/wiki/Q1644704","display_name":"MicroBlaze","level":3,"score":0.44072476029396057},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.43329474329948425},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.37056633830070496},{"id":"https://openalex.org/C78519656","wikidata":"https://www.wikidata.org/wiki/Q101333","display_name":"Mechanical engineering","level":1,"score":0.0},{"id":"https://openalex.org/C2524010","wikidata":"https://www.wikidata.org/wiki/Q8087","display_name":"Geometry","level":1,"score":0.0},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.0},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1145/1344671.1344683","is_oa":false,"landing_page_url":"https://doi.org/10.1145/1344671.1344683","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 16th international ACM/SIGDA symposium on Field programmable gate arrays","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"score":0.8199999928474426,"display_name":"Affordable and clean energy","id":"https://metadata.un.org/sdg/7"}],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":7,"referenced_works":["https://openalex.org/W1514655958","https://openalex.org/W2007317106","https://openalex.org/W2068347376","https://openalex.org/W2071724711","https://openalex.org/W2102182691","https://openalex.org/W2118443094","https://openalex.org/W2503863107"],"related_works":["https://openalex.org/W2586397364","https://openalex.org/W2532502681","https://openalex.org/W2108269296","https://openalex.org/W2163252286","https://openalex.org/W2053477252","https://openalex.org/W3085540031","https://openalex.org/W2494639327","https://openalex.org/W3171744009","https://openalex.org/W2041384801","https://openalex.org/W1910046164"],"abstract_inverted_index":{"Lithography":[0],"simulation,":[1],"as":[2],"an":[3,49],"essential":[4],"step":[5],"in":[6,94],"design":[7],"for":[8,37,74,137,141],"manufacturability":[9],"(DFM),":[10],"is":[11,34,67,114],"still":[12],"far":[13],"from":[14],"computationally":[15],"efficient.":[16],"Most":[17],"leading":[18],"companies":[19],"use":[20],"large":[21,76],"clusters":[22],"of":[23,51,78],"server":[24],"computers":[25],"to":[26,69],"achieve":[27],"acceptable":[28],"turn-around":[29],"time.":[30],"Thus":[31],"co-processor":[32],"acceleration":[33],"very":[35],"attractive":[36],"obtaining":[38],"increased":[39],"computational":[40],"performance":[41,118],"with":[42],"reduced":[43],"power":[44],"consumption.":[45],"This":[46],"paper":[47],"describes":[48],"implementation":[50,106,121],"a":[52,58,75,100,109],"customized":[53],"accelerator":[54],"on":[55,108],"FPGA":[56],"using":[57],"polygon-based":[59],"simulation":[60],"model.":[61],"An":[62],"application-specific":[63],"memory":[64],"partitioning":[65],"scheme":[66],"designed":[68],"meet":[70],"the":[71,104,129,135],"bandwidth":[72],"requirements":[73],"number":[77],"processing":[79],"elements.":[80],"Deep":[81],"loop":[82],"pipelining":[83,90],"and":[84,111],"ping-pong":[85],"buffer":[86],"based":[87],"function":[88],"block":[89],"are":[91],"also":[92,122,133],"implemented":[93],"our":[95],"design.":[96],"Initial":[97],"results":[98],"show":[99],"15X":[101],"speedup":[102,113],"versus":[103],"software":[105],"running":[107],"microprocessor,":[110],"more":[112],"expected":[115],"via":[116],"further":[117],"tuning.":[119],"The":[120],"leverages":[123],"state-of-art":[124],"C-to-RTL":[125],"synthesis":[126],"tools.":[127],"At":[128],"same":[130],"time,":[131],"we":[132],"identified":[134],"need":[136],"manual":[138],"architecture-level":[139],"exploration":[140],"parallel":[142],"implementations":[143]},"counts_by_year":[{"year":2016,"cited_by_count":1},{"year":2015,"cited_by_count":1},{"year":2013,"cited_by_count":3},{"year":2012,"cited_by_count":2}],"updated_date":"2026-07-29T14:22:42.915294","created_date":"2025-10-10T00:00:00"}