{"id":"https://openalex.org/W2027520315","doi":"https://doi.org/10.1145/1344671.1344679","title":"Beyond the arithmetic constraint","display_name":"Beyond the arithmetic constraint","publication_year":2008,"publication_date":"2008-02-24","ids":{"openalex":"https://openalex.org/W2027520315","doi":"https://doi.org/10.1145/1344671.1344679","mag":"2027520315"},"language":"en","primary_location":{"id":"doi:10.1145/1344671.1344679","is_oa":false,"landing_page_url":"https://doi.org/10.1145/1344671.1344679","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 16th international ACM/SIGDA symposium on Field programmable gate arrays","raw_type":"proceedings-article"},"type":"conference-paper","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5088071718","display_name":"M.T. Frederick","orcid":null},"institutions":[{"id":"https://openalex.org/I173911158","display_name":"Iowa State University","ror":"https://ror.org/04rswrd78","country_code":"US","type":"education","lineage":["https://openalex.org/I173911158"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Michael T. Frederick","raw_affiliation_strings":["Iowa State University, Ames, IA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Iowa State University, Ames, IA","institution_ids":["https://openalex.org/I173911158"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5087267932","display_name":"Arun K. Somani","orcid":"https://orcid.org/0000-0002-6248-4376"},"institutions":[{"id":"https://openalex.org/I173911158","display_name":"Iowa State University","ror":"https://ror.org/04rswrd78","country_code":"US","type":"education","lineage":["https://openalex.org/I173911158"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Arun K. Somani","raw_affiliation_strings":["Iowa State University, Ames, IA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Iowa State University, Ames, IA","institution_ids":["https://openalex.org/I173911158"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":1,"corresponding_author_ids":[],"corresponding_institution_ids":["https://openalex.org/I173911158"],"apc_list":null,"apc_paid":null,"fwci":2.8466,"has_fulltext":false,"cited_by_count":12,"citation_normalized_percentile":{"value":0.89933694,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":95},"biblio":{"volume":null,"issue":null,"first_page":"37","last_page":"46"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.994700014591217,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.994700014591217,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11269","display_name":"Algorithms and Data Compression","score":0.9848999977111816,"subfield":{"id":"https://openalex.org/subfields/1702","display_name":"Artificial Intelligence"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T12162","display_name":"Cellular Automata and Applications","score":0.9843999743461609,"subfield":{"id":"https://openalex.org/subfields/1703","display_name":"Computational Theory and Mathematics"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.6603822112083435},{"id":"https://openalex.org/keywords/arithmetic","display_name":"Arithmetic","score":0.6121228933334351},{"id":"https://openalex.org/keywords/constraint","display_name":"Constraint (computer-aided design)","score":0.5475276112556458},{"id":"https://openalex.org/keywords/programming-language","display_name":"Programming language","score":0.35219264030456543},{"id":"https://openalex.org/keywords/theoretical-computer-science","display_name":"Theoretical computer science","score":0.34647995233535767},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.3396558463573456},{"id":"https://openalex.org/keywords/mathematics","display_name":"Mathematics","score":0.21682727336883545}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6603822112083435},{"id":"https://openalex.org/C94375191","wikidata":"https://www.wikidata.org/wiki/Q11205","display_name":"Arithmetic","level":1,"score":0.6121228933334351},{"id":"https://openalex.org/C2776036281","wikidata":"https://www.wikidata.org/wiki/Q48769818","display_name":"Constraint (computer-aided design)","level":2,"score":0.5475276112556458},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.35219264030456543},{"id":"https://openalex.org/C80444323","wikidata":"https://www.wikidata.org/wiki/Q2878974","display_name":"Theoretical computer science","level":1,"score":0.34647995233535767},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.3396558463573456},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.21682727336883545},{"id":"https://openalex.org/C2524010","wikidata":"https://www.wikidata.org/wiki/Q8087","display_name":"Geometry","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1145/1344671.1344679","is_oa":false,"landing_page_url":"https://doi.org/10.1145/1344671.1344679","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 16th international ACM/SIGDA symposium on Field programmable gate arrays","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":8,"referenced_works":["https://openalex.org/W1511688816","https://openalex.org/W1964119857","https://openalex.org/W2105715355","https://openalex.org/W2113764809","https://openalex.org/W2121209623","https://openalex.org/W2136531659","https://openalex.org/W2159352256","https://openalex.org/W6781618339"],"related_works":["https://openalex.org/W2807251790","https://openalex.org/W2799406489","https://openalex.org/W2049792449","https://openalex.org/W2115140794","https://openalex.org/W986251431","https://openalex.org/W2503798035","https://openalex.org/W2041120224","https://openalex.org/W4249530125","https://openalex.org/W563727013","https://openalex.org/W1944601446"],"abstract_inverted_index":{"Look-up":[0],"table":[1],"based":[2],"FPGAs":[3,40],"have":[4,34],"migrated":[5],"from":[6],"a":[7,14,22],"niche":[8],"technology":[9],"for":[10,24],"design":[11],"prototyping":[12],"to":[13,77],"valuable":[15],"end-product":[16],"component":[17],"and,":[18],"in":[19,64],"some":[20],"cases,":[21],"replacement":[23],"general":[25],"purpose":[26],"processors":[27],"and":[28,41,55],"ASICs":[29,42],"alike.":[30],"One":[31],"way":[32],"architects":[33],"bridged":[35],"the":[36,45,68],"performance":[37],"gap":[38],"between":[39],"is":[43,67,74,90],"through":[44],"inclusion":[46],"of":[47],"specialized":[48],"components":[49],"such":[50],"as":[51,81],"multipliers,":[52],"RAM":[53],"modules,":[54],"microcontrollers.":[56],"Another":[57],"dedicated":[58],"structure":[59],"that":[60],"has":[61],"become":[62],"standard":[63],"reconfigurable":[65],"fabrics":[66],"arithmetic":[69,79],"carry":[70],"chain.":[71],"Currently,":[72],"it":[73,89],"only":[75],"used":[76],"map":[78],"operations":[80],"identified":[82],"by":[83],"HDL":[84],"macros.":[85],"For":[86],"non-arithmetic":[87],"operations,":[88],"an":[91],"idle":[92],"but":[93],"potentially":[94],"powerful":[95],"resource":[96]},"counts_by_year":[{"year":2021,"cited_by_count":2},{"year":2017,"cited_by_count":1},{"year":2015,"cited_by_count":1},{"year":2014,"cited_by_count":1},{"year":2012,"cited_by_count":1}],"updated_date":"2026-07-29T14:22:42.915294","created_date":"2025-10-10T00:00:00"}
