{"id":"https://openalex.org/W1977505713","doi":"https://doi.org/10.1145/1331897.1331900","title":"Statistical Analysis and Process Variation-Aware Routing and Skew Assignment for FPGAs","display_name":"Statistical Analysis and Process Variation-Aware Routing and Skew Assignment for FPGAs","publication_year":2008,"publication_date":"2008-03-01","ids":{"openalex":"https://openalex.org/W1977505713","doi":"https://doi.org/10.1145/1331897.1331900","mag":"1977505713"},"language":"en","primary_location":{"id":"doi:10.1145/1331897.1331900","is_oa":false,"landing_page_url":"https://doi.org/10.1145/1331897.1331900","pdf_url":null,"source":{"id":"https://openalex.org/S112809824","display_name":"ACM Transactions on Reconfigurable Technology and Systems","issn_l":"1936-7406","issn":["1936-7406","1936-7414"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319798","host_organization_name":"Association for Computing Machinery","host_organization_lineage":["https://openalex.org/P4310319798"],"host_organization_lineage_names":["Association for Computing Machinery"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"ACM Transactions on Reconfigurable Technology and Systems","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5025849840","display_name":"Satish Sivaswamy","orcid":null},"institutions":[{"id":"https://openalex.org/I2800403580","display_name":"University of Minnesota System","ror":"https://ror.org/03grvy078","country_code":"US","type":"education","lineage":["https://openalex.org/I2800403580"]}],"countries":["US"],"is_corresponding":true,"raw_author_name":"Satish Sivaswamy","raw_affiliation_strings":["University of Minnesota"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"University of Minnesota","institution_ids":["https://openalex.org/I2800403580"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5013257804","display_name":"Kia Bazargan","orcid":"https://orcid.org/0000-0003-3624-7366"},"institutions":[{"id":"https://openalex.org/I2800403580","display_name":"University of Minnesota System","ror":"https://ror.org/03grvy078","country_code":"US","type":"education","lineage":["https://openalex.org/I2800403580"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Kia Bazargan","raw_affiliation_strings":["University of Minnesota"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"University of Minnesota","institution_ids":["https://openalex.org/I2800403580"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":2,"corresponding_author_ids":["https://openalex.org/A5025849840"],"corresponding_institution_ids":["https://openalex.org/I2800403580"],"apc_list":null,"apc_paid":null,"fwci":2.374,"has_fulltext":false,"cited_by_count":16,"citation_normalized_percentile":{"value":0.87965283,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":90,"max":98},"biblio":{"volume":"1","issue":"1","first_page":"1","last_page":"35"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.8149120807647705},{"id":"https://openalex.org/keywords/skew","display_name":"Skew","score":0.7750378251075745},{"id":"https://openalex.org/keywords/clock-network","display_name":"Clock network","score":0.7229930758476257},{"id":"https://openalex.org/keywords/process-variation","display_name":"Process variation","score":0.6909135580062866},{"id":"https://openalex.org/keywords/routing","display_name":"Routing (electronic design automation)","score":0.6354831457138062},{"id":"https://openalex.org/keywords/router","display_name":"Router","score":0.6161381006240845},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.5783290863037109},{"id":"https://openalex.org/keywords/static-timing-analysis","display_name":"Static timing analysis","score":0.5362498164176941},{"id":"https://openalex.org/keywords/process","display_name":"Process (computing)","score":0.5325618982315063},{"id":"https://openalex.org/keywords/placement","display_name":"Placement","score":0.4728277623653412},{"id":"https://openalex.org/keywords/variation","display_name":"Variation (astronomy)","score":0.4581136107444763},{"id":"https://openalex.org/keywords/reduction","display_name":"Reduction (mathematics)","score":0.44878318905830383},{"id":"https://openalex.org/keywords/timing-failure","display_name":"Timing failure","score":0.41768965125083923},{"id":"https://openalex.org/keywords/clock-skew","display_name":"Clock skew","score":0.3936251401901245},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.3633291721343994},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.3541381061077118},{"id":"https://openalex.org/keywords/physical-design","display_name":"Physical design","score":0.21708634495735168},{"id":"https://openalex.org/keywords/circuit-design","display_name":"Circuit design","score":0.18405434489250183},{"id":"https://openalex.org/keywords/computer-network","display_name":"Computer network","score":0.14786982536315918},{"id":"https://openalex.org/keywords/mathematics","display_name":"Mathematics","score":0.08979496359825134},{"id":"https://openalex.org/keywords/telecommunications","display_name":"Telecommunications","score":0.08480584621429443}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.8149120807647705},{"id":"https://openalex.org/C43711488","wikidata":"https://www.wikidata.org/wiki/Q7534783","display_name":"Skew","level":2,"score":0.7750378251075745},{"id":"https://openalex.org/C2778182565","wikidata":"https://www.wikidata.org/wiki/Q1752879","display_name":"Clock network","level":5,"score":0.7229930758476257},{"id":"https://openalex.org/C93389723","wikidata":"https://www.wikidata.org/wiki/Q7247313","display_name":"Process variation","level":3,"score":0.6909135580062866},{"id":"https://openalex.org/C74172769","wikidata":"https://www.wikidata.org/wiki/Q1446839","display_name":"Routing (electronic design automation)","level":2,"score":0.6354831457138062},{"id":"https://openalex.org/C2775896111","wikidata":"https://www.wikidata.org/wiki/Q642560","display_name":"Router","level":2,"score":0.6161381006240845},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.5783290863037109},{"id":"https://openalex.org/C93682380","wikidata":"https://www.wikidata.org/wiki/Q2025226","display_name":"Static timing analysis","level":2,"score":0.5362498164176941},{"id":"https://openalex.org/C98045186","wikidata":"https://www.wikidata.org/wiki/Q205663","display_name":"Process (computing)","level":2,"score":0.5325618982315063},{"id":"https://openalex.org/C117690923","wikidata":"https://www.wikidata.org/wiki/Q1484784","display_name":"Placement","level":4,"score":0.4728277623653412},{"id":"https://openalex.org/C2778334786","wikidata":"https://www.wikidata.org/wiki/Q1586270","display_name":"Variation (astronomy)","level":2,"score":0.4581136107444763},{"id":"https://openalex.org/C111335779","wikidata":"https://www.wikidata.org/wiki/Q3454686","display_name":"Reduction (mathematics)","level":2,"score":0.44878318905830383},{"id":"https://openalex.org/C104654189","wikidata":"https://www.wikidata.org/wiki/Q7806740","display_name":"Timing failure","level":5,"score":0.41768965125083923},{"id":"https://openalex.org/C60501442","wikidata":"https://www.wikidata.org/wiki/Q4382014","display_name":"Clock skew","level":4,"score":0.3936251401901245},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.3633291721343994},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.3541381061077118},{"id":"https://openalex.org/C188817802","wikidata":"https://www.wikidata.org/wiki/Q13426855","display_name":"Physical design","level":3,"score":0.21708634495735168},{"id":"https://openalex.org/C190560348","wikidata":"https://www.wikidata.org/wiki/Q3245116","display_name":"Circuit design","level":2,"score":0.18405434489250183},{"id":"https://openalex.org/C31258907","wikidata":"https://www.wikidata.org/wiki/Q1301371","display_name":"Computer network","level":1,"score":0.14786982536315918},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.08979496359825134},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.08480584621429443},{"id":"https://openalex.org/C2524010","wikidata":"https://www.wikidata.org/wiki/Q8087","display_name":"Geometry","level":1,"score":0.0},{"id":"https://openalex.org/C134652429","wikidata":"https://www.wikidata.org/wiki/Q1052698","display_name":"Jitter","level":2,"score":0.0},{"id":"https://openalex.org/C121332964","wikidata":"https://www.wikidata.org/wiki/Q413","display_name":"Physics","level":0,"score":0.0},{"id":"https://openalex.org/C44870925","wikidata":"https://www.wikidata.org/wiki/Q37547","display_name":"Astrophysics","level":1,"score":0.0},{"id":"https://openalex.org/C137059387","wikidata":"https://www.wikidata.org/wiki/Q426882","display_name":"Clock signal","level":3,"score":0.0},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1145/1331897.1331900","is_oa":false,"landing_page_url":"https://doi.org/10.1145/1331897.1331900","pdf_url":null,"source":{"id":"https://openalex.org/S112809824","display_name":"ACM Transactions on Reconfigurable Technology and Systems","issn_l":"1936-7406","issn":["1936-7406","1936-7414"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319798","host_organization_name":"Association for Computing Machinery","host_organization_lineage":["https://openalex.org/P4310319798"],"host_organization_lineage_names":["Association for Computing Machinery"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"ACM Transactions on Reconfigurable Technology and Systems","raw_type":"journal-article"}],"best_oa_location":null,"sustainable_development_goals":[{"score":0.47999998927116394,"id":"https://metadata.un.org/sdg/9","display_name":"Industry, innovation and infrastructure"}],"awards":[{"id":"https://openalex.org/G920906124","display_name":null,"funder_award_id":"CCF-0347891","funder_id":"https://openalex.org/F4320337387","funder_display_name":"Division of Computing and Communication Foundations"}],"funders":[{"id":"https://openalex.org/F4320337387","display_name":"Division of Computing and Communication Foundations","ror":"https://ror.org/01mng8331"}],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":27,"referenced_works":["https://openalex.org/W3381706","https://openalex.org/W1523051745","https://openalex.org/W1558331362","https://openalex.org/W1693570377","https://openalex.org/W1963746503","https://openalex.org/W1997797456","https://openalex.org/W2049960281","https://openalex.org/W2084083833","https://openalex.org/W2095558812","https://openalex.org/W2100362001","https://openalex.org/W2110687226","https://openalex.org/W2114834460","https://openalex.org/W2115596773","https://openalex.org/W2118482092","https://openalex.org/W2119125081","https://openalex.org/W2132554587","https://openalex.org/W2133111265","https://openalex.org/W2135097932","https://openalex.org/W2136328167","https://openalex.org/W2141682861","https://openalex.org/W2157406114","https://openalex.org/W2158750015","https://openalex.org/W2160181362","https://openalex.org/W2163262735","https://openalex.org/W2603178913","https://openalex.org/W2913252637","https://openalex.org/W4234168281"],"related_works":["https://openalex.org/W4247180033","https://openalex.org/W2144282137","https://openalex.org/W2088914741","https://openalex.org/W2559451387","https://openalex.org/W2087612346","https://openalex.org/W4247860997","https://openalex.org/W2617666058","https://openalex.org/W2154194029","https://openalex.org/W4239208108","https://openalex.org/W2163899785"],"abstract_inverted_index":{"With":[0],"constant":[1],"scaling":[2],"of":[3,27,41,61,136],"process":[4,14],"technologies,":[5],"chip":[6],"design":[7],"is":[8,98,119],"becoming":[9],"increasingly":[10],"difficult":[11],"due":[12],"to":[13,37,46,57,78,82,86,107,121],"variations.":[15,28,62],"The":[16],"FPGA":[17],"community":[18],"has":[19],"only":[20],"recently":[21],"started":[22],"focusing":[23],"on":[24,43],"the":[25,39,59,79,92,96,115],"effects":[26,40],"In":[29],"this":[30],"work":[31],"we":[32,64,90],"present":[33,52,65],"a":[34,66,76,99,108,133,140],"statistical":[35,71,125],"analysis":[36],"compare":[38],"variations":[42],"designs":[44],"mapped":[45],"FPGAs":[47],"and":[48,54,95,127],"ASICs.":[49],"We":[50,73],"also":[51],"CAD":[53],"architecture":[55],"techniques":[56,94],"mitigate":[58],"impact":[60],"First":[63],"variation-aware":[67],"router":[68],"that":[69,105],"optimizes":[70],"criticality.":[72],"then":[74],"propose":[75],"modification":[77],"clock":[80],"network":[81],"deliver":[83],"programmable":[84],"skews":[85],"different":[87],"flip-flops.":[88],"Finally,":[89],"combine":[91],"two":[93],"result":[97],"9x":[100],"reduction":[101],"in":[102,111,132],"yield":[103,118],"loss":[104],"translates":[106],"12%":[109],"improvement":[110,135],"timing":[112,117],"yield.":[113],"When":[114],"desired":[116],"set":[120],"99%,":[122],"our":[123],"combined":[124],"routing":[126],"skew":[128],"assignment":[129],"technique":[130],"results":[131],"delay":[134],"about":[137],"10%":[138],"over":[139],"purely":[141],"deterministic":[142],"approach.":[143]},"counts_by_year":[{"year":2016,"cited_by_count":1},{"year":2015,"cited_by_count":1},{"year":2014,"cited_by_count":4},{"year":2013,"cited_by_count":2},{"year":2012,"cited_by_count":1}],"updated_date":"2026-05-21T06:26:12.895304","created_date":"2025-10-10T00:00:00"}
