{"id":"https://openalex.org/W2105231259","doi":"https://doi.org/10.1145/1328408.1328416","title":"Synthesizable high level hardware descriptions","display_name":"Synthesizable high level hardware descriptions","publication_year":2008,"publication_date":"2008-01-07","ids":{"openalex":"https://openalex.org/W2105231259","doi":"https://doi.org/10.1145/1328408.1328416","mag":"2105231259"},"language":"en","primary_location":{"id":"doi:10.1145/1328408.1328416","is_oa":false,"landing_page_url":"https://doi.org/10.1145/1328408.1328416","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 2008 ACM SIGPLAN symposium on Partial evaluation and semantics-based program manipulation","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5069012220","display_name":"Jennifer Gillenwater","orcid":null},"institutions":[{"id":"https://openalex.org/I74775410","display_name":"Rice University","ror":"https://ror.org/008zs3103","country_code":"US","type":"education","lineage":["https://openalex.org/I74775410"]}],"countries":["US"],"is_corresponding":true,"raw_author_name":"Jennifer Gillenwater","raw_affiliation_strings":["Rice University, Houston, TX","Rice University (Houston, TX)"],"affiliations":[{"raw_affiliation_string":"Rice University, Houston, TX","institution_ids":["https://openalex.org/I74775410"]},{"raw_affiliation_string":"Rice University (Houston, TX)","institution_ids":["https://openalex.org/I74775410"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5076825131","display_name":"Gregory Malecha","orcid":"https://orcid.org/0000-0003-3952-0807"},"institutions":[{"id":"https://openalex.org/I74775410","display_name":"Rice University","ror":"https://ror.org/008zs3103","country_code":"US","type":"education","lineage":["https://openalex.org/I74775410"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Gregory Malecha","raw_affiliation_strings":["Rice University, Houston, TX","Rice University (Houston, TX)"],"affiliations":[{"raw_affiliation_string":"Rice University, Houston, TX","institution_ids":["https://openalex.org/I74775410"]},{"raw_affiliation_string":"Rice University (Houston, TX)","institution_ids":["https://openalex.org/I74775410"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5083383825","display_name":"Cherif Salama","orcid":"https://orcid.org/0000-0002-6986-4697"},"institutions":[{"id":"https://openalex.org/I74775410","display_name":"Rice University","ror":"https://ror.org/008zs3103","country_code":"US","type":"education","lineage":["https://openalex.org/I74775410"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Cherif Salama","raw_affiliation_strings":["Rice University, Houston, TX","Rice University (Houston, TX)"],"affiliations":[{"raw_affiliation_string":"Rice University, Houston, TX","institution_ids":["https://openalex.org/I74775410"]},{"raw_affiliation_string":"Rice University (Houston, TX)","institution_ids":["https://openalex.org/I74775410"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5057201397","display_name":"Angela Yun Zhu","orcid":null},"institutions":[{"id":"https://openalex.org/I74775410","display_name":"Rice University","ror":"https://ror.org/008zs3103","country_code":"US","type":"education","lineage":["https://openalex.org/I74775410"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Angela Yun Zhu","raw_affiliation_strings":["Rice University, Houston, TX","Rice University (Houston, TX)"],"affiliations":[{"raw_affiliation_string":"Rice University, Houston, TX","institution_ids":["https://openalex.org/I74775410"]},{"raw_affiliation_string":"Rice University (Houston, TX)","institution_ids":["https://openalex.org/I74775410"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5008976751","display_name":"Walid Taha","orcid":"https://orcid.org/0000-0003-3160-9188"},"institutions":[{"id":"https://openalex.org/I74775410","display_name":"Rice University","ror":"https://ror.org/008zs3103","country_code":"US","type":"education","lineage":["https://openalex.org/I74775410"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Walid Taha","raw_affiliation_strings":["Rice University, Houston, TX","Rice University (Houston, TX)"],"affiliations":[{"raw_affiliation_string":"Rice University, Houston, TX","institution_ids":["https://openalex.org/I74775410"]},{"raw_affiliation_string":"Rice University (Houston, TX)","institution_ids":["https://openalex.org/I74775410"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5040867461","display_name":"Jim Grundy","orcid":null},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Jim Grundy","raw_affiliation_strings":["Intel Strategic CAD Labs, Portland, OR","Intel Strategic CAD Labs, Portland, OR#TAB#"],"affiliations":[{"raw_affiliation_string":"Intel Strategic CAD Labs, Portland, OR","institution_ids":["https://openalex.org/I1343180700"]},{"raw_affiliation_string":"Intel Strategic CAD Labs, Portland, OR#TAB#","institution_ids":["https://openalex.org/I1343180700"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5105768200","display_name":"John O\u2019Leary","orcid":"https://orcid.org/0000-0001-9327-5852"},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"John O'Leary","raw_affiliation_strings":["Intel Strategic CAD Labs, Portland, OR","Intel Strategic CAD Labs, Portland, OR#TAB#"],"affiliations":[{"raw_affiliation_string":"Intel Strategic CAD Labs, Portland, OR","institution_ids":["https://openalex.org/I1343180700"]},{"raw_affiliation_string":"Intel Strategic CAD Labs, Portland, OR#TAB#","institution_ids":["https://openalex.org/I1343180700"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":7,"corresponding_author_ids":["https://openalex.org/A5069012220"],"corresponding_institution_ids":["https://openalex.org/I74775410"],"apc_list":null,"apc_paid":null,"fwci":3.1,"has_fulltext":false,"cited_by_count":15,"citation_normalized_percentile":{"value":0.92005143,"is_in_top_1_percent":false,"is_in_top_10_percent":true},"cited_by_percentile_year":{"min":90,"max":96},"biblio":{"volume":null,"issue":null,"first_page":"41","last_page":"50"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10142","display_name":"Formal Methods in Verification","score":0.9991999864578247,"subfield":{"id":"https://openalex.org/subfields/1703","display_name":"Computational Theory and Mathematics"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.8211351633071899},{"id":"https://openalex.org/keywords/verilog","display_name":"Verilog","score":0.7069954872131348},{"id":"https://openalex.org/keywords/hardware-description-language","display_name":"Hardware description language","score":0.7068089842796326},{"id":"https://openalex.org/keywords/vhdl","display_name":"VHDL","score":0.664046049118042},{"id":"https://openalex.org/keywords/parameterized-complexity","display_name":"Parameterized complexity","score":0.6274729371070862},{"id":"https://openalex.org/keywords/programming-language","display_name":"Programming language","score":0.5827878713607788},{"id":"https://openalex.org/keywords/code","display_name":"Code (set theory)","score":0.5540673136711121},{"id":"https://openalex.org/keywords/code-generation","display_name":"Code generation","score":0.5362673401832581},{"id":"https://openalex.org/keywords/process","display_name":"Process (computing)","score":0.5329791903495789},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.5110820531845093},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.49319928884506226},{"id":"https://openalex.org/keywords/register-transfer-level","display_name":"Register-transfer level","score":0.4850015342235565},{"id":"https://openalex.org/keywords/high-level-synthesis","display_name":"High-level synthesis","score":0.42932796478271484},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.3750392496585846},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.35568922758102417},{"id":"https://openalex.org/keywords/logic-synthesis","display_name":"Logic synthesis","score":0.33151084184646606},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.32754647731781006},{"id":"https://openalex.org/keywords/logic-gate","display_name":"Logic gate","score":0.2368861734867096},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.1231812834739685},{"id":"https://openalex.org/keywords/operating-system","display_name":"Operating system","score":0.12211951613426208},{"id":"https://openalex.org/keywords/key","display_name":"Key (lock)","score":0.07847410440444946}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.8211351633071899},{"id":"https://openalex.org/C2779030575","wikidata":"https://www.wikidata.org/wiki/Q827773","display_name":"Verilog","level":3,"score":0.7069954872131348},{"id":"https://openalex.org/C42143788","wikidata":"https://www.wikidata.org/wiki/Q173341","display_name":"Hardware description language","level":3,"score":0.7068089842796326},{"id":"https://openalex.org/C36941000","wikidata":"https://www.wikidata.org/wiki/Q209455","display_name":"VHDL","level":3,"score":0.664046049118042},{"id":"https://openalex.org/C165464430","wikidata":"https://www.wikidata.org/wiki/Q1570441","display_name":"Parameterized complexity","level":2,"score":0.6274729371070862},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.5827878713607788},{"id":"https://openalex.org/C2776760102","wikidata":"https://www.wikidata.org/wiki/Q5139990","display_name":"Code (set theory)","level":3,"score":0.5540673136711121},{"id":"https://openalex.org/C133162039","wikidata":"https://www.wikidata.org/wiki/Q1061077","display_name":"Code generation","level":3,"score":0.5362673401832581},{"id":"https://openalex.org/C98045186","wikidata":"https://www.wikidata.org/wiki/Q205663","display_name":"Process (computing)","level":2,"score":0.5329791903495789},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.5110820531845093},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.49319928884506226},{"id":"https://openalex.org/C34854456","wikidata":"https://www.wikidata.org/wiki/Q1484552","display_name":"Register-transfer level","level":4,"score":0.4850015342235565},{"id":"https://openalex.org/C58013763","wikidata":"https://www.wikidata.org/wiki/Q5754574","display_name":"High-level synthesis","level":3,"score":0.42932796478271484},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.3750392496585846},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.35568922758102417},{"id":"https://openalex.org/C157922185","wikidata":"https://www.wikidata.org/wiki/Q173198","display_name":"Logic synthesis","level":3,"score":0.33151084184646606},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.32754647731781006},{"id":"https://openalex.org/C131017901","wikidata":"https://www.wikidata.org/wiki/Q170451","display_name":"Logic gate","level":2,"score":0.2368861734867096},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.1231812834739685},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.12211951613426208},{"id":"https://openalex.org/C26517878","wikidata":"https://www.wikidata.org/wiki/Q228039","display_name":"Key (lock)","level":2,"score":0.07847410440444946},{"id":"https://openalex.org/C177264268","wikidata":"https://www.wikidata.org/wiki/Q1514741","display_name":"Set (abstract data type)","level":2,"score":0.0}],"mesh":[],"locations_count":3,"locations":[{"id":"doi:10.1145/1328408.1328416","is_oa":false,"landing_page_url":"https://doi.org/10.1145/1328408.1328416","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 2008 ACM SIGPLAN symposium on Partial evaluation and semantics-based program manipulation","raw_type":"proceedings-article"},{"id":"pmh:oai:CiteSeerX.psu:10.1.1.102.9458","is_oa":false,"landing_page_url":"http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.102.9458","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"http://www.texbot.org/twiki/pub/RAP/VPP/FV-TR.pdf","raw_type":"text"},{"id":"pmh:oai:CiteSeerX.psu:10.1.1.157.6856","is_oa":false,"landing_page_url":"http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.157.6856","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"http://www.cs.rice.edu/~taha/publications/conference/pepm08.pdf","raw_type":"text"}],"best_oa_location":null,"sustainable_development_goals":[{"score":0.4000000059604645,"id":"https://metadata.un.org/sdg/9","display_name":"Industry, innovation and infrastructure"}],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":16,"referenced_works":["https://openalex.org/W598205067","https://openalex.org/W616429135","https://openalex.org/W635909831","https://openalex.org/W1583453248","https://openalex.org/W1600978471","https://openalex.org/W1777933108","https://openalex.org/W2029786195","https://openalex.org/W2036753530","https://openalex.org/W2059019165","https://openalex.org/W2073378225","https://openalex.org/W2154273644","https://openalex.org/W2171433297","https://openalex.org/W2561675875","https://openalex.org/W4236051643","https://openalex.org/W4238977241","https://openalex.org/W6638203772"],"related_works":["https://openalex.org/W2366672283","https://openalex.org/W2168113051","https://openalex.org/W4233828762","https://openalex.org/W2389932690","https://openalex.org/W2916312349","https://openalex.org/W2145843790","https://openalex.org/W2097236935","https://openalex.org/W127546600","https://openalex.org/W4214657400","https://openalex.org/W2153401337"],"abstract_inverted_index":{"Modern":[0],"hardware":[1,20,28],"description":[2],"languages":[3],"support":[4],"code-generation":[5],"constructs":[6,12,42],"like":[7],"generate/endgenerate":[8],"in":[9],"Verilog.":[10],"These":[11],"are":[13],"intended":[14],"to":[15,47,82,103],"describe":[16],"regular":[17],"or":[18],"parameterized":[19],"designs":[21],"and,":[22],"when":[23],"used":[24],"effectively,":[25],"can":[26],"make":[27],"descriptions":[29],"shorter,":[30],"more":[31,34],"understandable,":[32],"and":[33,49,73,95],"reusable.":[35],"In":[36,92],"practice,":[37],"however,":[38],"designers":[39],"avoid":[40],"these":[41,84],"because":[43],"it":[44,65,76],"is":[45,79,101],"difficult":[46],"understand":[48],"predict":[50],"the":[51,54,58,89,93],"properties":[52],"of":[53],"generated":[55,59],"code.":[56,91],"Is":[57,64],"code":[60],"even":[61],"type":[62],"safe?":[63],"synthesizable?":[66],"What":[67],"physical":[68],"resources":[69],"(e.g.":[70],"combinatorial":[71],"gates":[72],"flip-flops)":[74],"does":[75],"require?":[77],"It":[78],"often":[80],"impossible":[81],"answer":[83],"questions":[85],"without":[86],"first":[87],"generating":[88],"fully-expanded":[90],"Verilog":[94],"VHDL":[96],"communities,":[97],"this":[98],"generation":[99],"process":[100],"referred":[102],"as":[104],"elaboration.":[105]},"counts_by_year":[{"year":2023,"cited_by_count":1},{"year":2016,"cited_by_count":2},{"year":2015,"cited_by_count":1},{"year":2012,"cited_by_count":2}],"updated_date":"2026-04-04T16:13:02.066488","created_date":"2025-10-10T00:00:00"}
