{"id":"https://openalex.org/W2089583925","doi":"https://doi.org/10.1145/1294313.1294320","title":"Improving instruction level parallelism through reconfigurable units in superscalar processors","display_name":"Improving instruction level parallelism through reconfigurable units in superscalar processors","publication_year":2007,"publication_date":"2007-06-01","ids":{"openalex":"https://openalex.org/W2089583925","doi":"https://doi.org/10.1145/1294313.1294320","mag":"2089583925"},"language":"en","primary_location":{"id":"doi:10.1145/1294313.1294320","is_oa":false,"landing_page_url":"https://doi.org/10.1145/1294313.1294320","pdf_url":null,"source":{"id":"https://openalex.org/S4210193905","display_name":"ACM SIGARCH Computer Architecture News","issn_l":"0163-5964","issn":["0163-5964","1943-5851"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310320740","host_organization_name":"ACM SIGARCH","host_organization_lineage":["https://openalex.org/P4310320740"],"host_organization_lineage_names":["ACM SIGARCH"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"ACM SIGARCH Computer Architecture News","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5074941650","display_name":"Tameesh Suri","orcid":null},"institutions":[{"id":"https://openalex.org/I123946342","display_name":"Binghamton University","ror":"https://ror.org/008rmbt77","country_code":"US","type":"education","lineage":["https://openalex.org/I123946342"]}],"countries":["US"],"is_corresponding":true,"raw_author_name":"Tameesh Suri","raw_affiliation_strings":["State University of New York at Binghamton, NY","State University of New York at Binghamton, NY#TAB#"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"State University of New York at Binghamton, NY","institution_ids":["https://openalex.org/I123946342"]},{"raw_affiliation_string":"State University of New York at Binghamton, NY#TAB#","institution_ids":["https://openalex.org/I123946342"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":1,"corresponding_author_ids":["https://openalex.org/A5074941650"],"corresponding_institution_ids":["https://openalex.org/I123946342"],"apc_list":null,"apc_paid":null,"fwci":0.3183,"has_fulltext":false,"cited_by_count":1,"citation_normalized_percentile":{"value":0.63158902,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":"35","issue":"3","first_page":"20","last_page":"27"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.9995999932289124,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.8366315960884094},{"id":"https://openalex.org/keywords/datapath","display_name":"Datapath","score":0.8340688943862915},{"id":"https://openalex.org/keywords/superscalar","display_name":"Superscalar","score":0.727141797542572},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.6974036693572998},{"id":"https://openalex.org/keywords/instruction-level-parallelism","display_name":"Instruction-level parallelism","score":0.5380041599273682},{"id":"https://openalex.org/keywords/control-reconfiguration","display_name":"Control reconfiguration","score":0.5343389511108398},{"id":"https://openalex.org/keywords/branch-predictor","display_name":"Branch predictor","score":0.5269566178321838},{"id":"https://openalex.org/keywords/queue","display_name":"Queue","score":0.4506058692932129},{"id":"https://openalex.org/keywords/trace","display_name":"TRACE (psycholinguistics)","score":0.44607239961624146},{"id":"https://openalex.org/keywords/speculative-execution","display_name":"Speculative execution","score":0.4203779101371765},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.35977792739868164},{"id":"https://openalex.org/keywords/parallelism","display_name":"Parallelism (grammar)","score":0.3546779453754425},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.23831087350845337},{"id":"https://openalex.org/keywords/programming-language","display_name":"Programming language","score":0.0711686909198761}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.8366315960884094},{"id":"https://openalex.org/C2781198647","wikidata":"https://www.wikidata.org/wiki/Q1633673","display_name":"Datapath","level":2,"score":0.8340688943862915},{"id":"https://openalex.org/C147101560","wikidata":"https://www.wikidata.org/wiki/Q1045706","display_name":"Superscalar","level":2,"score":0.727141797542572},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.6974036693572998},{"id":"https://openalex.org/C140763907","wikidata":"https://www.wikidata.org/wiki/Q2714055","display_name":"Instruction-level parallelism","level":3,"score":0.5380041599273682},{"id":"https://openalex.org/C119701452","wikidata":"https://www.wikidata.org/wiki/Q5165881","display_name":"Control reconfiguration","level":2,"score":0.5343389511108398},{"id":"https://openalex.org/C168522837","wikidata":"https://www.wikidata.org/wiki/Q679552","display_name":"Branch predictor","level":2,"score":0.5269566178321838},{"id":"https://openalex.org/C160403385","wikidata":"https://www.wikidata.org/wiki/Q220543","display_name":"Queue","level":2,"score":0.4506058692932129},{"id":"https://openalex.org/C75291252","wikidata":"https://www.wikidata.org/wiki/Q1315756","display_name":"TRACE (psycholinguistics)","level":2,"score":0.44607239961624146},{"id":"https://openalex.org/C141331961","wikidata":"https://www.wikidata.org/wiki/Q2164465","display_name":"Speculative execution","level":2,"score":0.4203779101371765},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.35977792739868164},{"id":"https://openalex.org/C2781172179","wikidata":"https://www.wikidata.org/wiki/Q853109","display_name":"Parallelism (grammar)","level":2,"score":0.3546779453754425},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.23831087350845337},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.0711686909198761},{"id":"https://openalex.org/C41895202","wikidata":"https://www.wikidata.org/wiki/Q8162","display_name":"Linguistics","level":1,"score":0.0},{"id":"https://openalex.org/C138885662","wikidata":"https://www.wikidata.org/wiki/Q5891","display_name":"Philosophy","level":0,"score":0.0}],"mesh":[],"locations_count":2,"locations":[{"id":"doi:10.1145/1294313.1294320","is_oa":false,"landing_page_url":"https://doi.org/10.1145/1294313.1294320","pdf_url":null,"source":{"id":"https://openalex.org/S4210193905","display_name":"ACM SIGARCH Computer Architecture News","issn_l":"0163-5964","issn":["0163-5964","1943-5851"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310320740","host_organization_name":"ACM SIGARCH","host_organization_lineage":["https://openalex.org/P4310320740"],"host_organization_lineage_names":["ACM SIGARCH"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"ACM SIGARCH Computer Architecture News","raw_type":"journal-article"},{"id":"pmh:oai:CiteSeerX.psu:10.1.1.116.9437","is_oa":false,"landing_page_url":"http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.116.9437","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"http://bingweb.binghamton.edu/~tsuri1/RAAW_TSuri_2006.pdf","raw_type":"text"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":18,"referenced_works":["https://openalex.org/W286049110","https://openalex.org/W1974169079","https://openalex.org/W2008165887","https://openalex.org/W2025787141","https://openalex.org/W2028285139","https://openalex.org/W2028922196","https://openalex.org/W2051612220","https://openalex.org/W2083868341","https://openalex.org/W2112438883","https://openalex.org/W2131176628","https://openalex.org/W2142490124","https://openalex.org/W2146188244","https://openalex.org/W2148911285","https://openalex.org/W2155509874","https://openalex.org/W2156274518","https://openalex.org/W2169996458","https://openalex.org/W3146150975","https://openalex.org/W4250370106"],"related_works":["https://openalex.org/W1977470888","https://openalex.org/W2131679972","https://openalex.org/W2024285967","https://openalex.org/W2408058673","https://openalex.org/W2053687647","https://openalex.org/W2113960387","https://openalex.org/W1595275176","https://openalex.org/W2085860917","https://openalex.org/W1788425660","https://openalex.org/W1498421039"],"abstract_inverted_index":{"With":[0,146],"reducing":[1],"feature":[2],"sizes,":[3],"more":[4],"transistors":[5,32],"can":[6,16],"be":[7,17,34],"integrated":[8],"on":[9,107],"the":[10,21,28,31,39,45,59,77,88,93,96,99,105,108,114,118,122,124,162],"chip.":[11],"The":[12,70],"increased":[13],"transistor":[14],"budget":[15],"utilized":[18],"to":[19,36,75,103],"improve":[20],"instruction":[22],"level":[23],"parallelism":[24],"(ILP)":[25],"exploited":[26],"from":[27],"processor.":[29],"However,":[30],"cannot":[33],"used":[35],"arbitrarily":[37],"increase":[38],"processor":[40],"width":[41],"and":[42,98],"size":[43],"in":[44,95,121],"hope":[46],"of":[47,79,158],"exploiting":[48],"better":[49],"ILP.":[50],"In":[51,128],"this":[52,129,147],"paper,":[53],"we":[54,101,149],"propose":[55,102],"an":[56,151],"architecture":[57],"where":[58],"superscalar":[60,97],"datapath":[61],"is":[62,73,133,142],"tightly":[63],"coupled":[64],"with":[65,110],"a":[66,168],"reconfigurable":[67],"unit":[68,72],"(RFU).":[69],"reconfiguration":[71],"configured":[74],"execute":[76,104],"traces":[78],"dynamic":[80],"instructions":[81,94,116,153],"that":[82],"are":[83,126],"frequently":[84],"executed.":[85],"To":[86],"address":[87],"data":[89,173],"dependency":[90],"issues":[91],"between":[92],"RFU,":[100],"trace":[106,115],"RFU":[109],"predicted":[111],"values.":[112],"When":[113],"reach":[117],"issue":[119],"queue":[120],"superscalar,":[123],"predictions":[125],"validated.":[127],"technique,":[130],"performance":[131,140],"improvement":[132,157],"obtained":[134],"for":[135,144],"correct":[136],"prediction,":[137],"whereas":[138],"no":[139],"degradation":[141],"incurred":[143],"mispredictions.":[145],"architecture,":[148],"observe":[150],"average":[152],"per":[154],"cycle":[155],"(IPC)":[156],"about":[159],"11%":[160],"over":[161],"simulated":[163],"SPEC":[164],"2000":[165],"benchmarks,":[166],"using":[167],"very":[169],"small":[170],"last":[171],"value":[172,174],"predictor.":[175]},"counts_by_year":[],"updated_date":"2026-05-21T09:19:25.381259","created_date":"2025-10-10T00:00:00"}