{"id":"https://openalex.org/W2098139685","doi":"https://doi.org/10.1145/1289881.1289912","title":"Facilitating compiler optimizations through the dynamic mapping of alternate register structures","display_name":"Facilitating compiler optimizations through the dynamic mapping of alternate register structures","publication_year":2007,"publication_date":"2007-09-30","ids":{"openalex":"https://openalex.org/W2098139685","doi":"https://doi.org/10.1145/1289881.1289912","mag":"2098139685"},"language":"en","primary_location":{"id":"doi:10.1145/1289881.1289912","is_oa":false,"landing_page_url":"https://doi.org/10.1145/1289881.1289912","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 2007 international conference on Compilers, architecture, and synthesis for embedded systems","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5037422850","display_name":"Christopher Zimmer","orcid":"https://orcid.org/0000-0001-5054-4354"},"institutions":[{"id":"https://openalex.org/I103163165","display_name":"Florida State University","ror":"https://ror.org/05g3dte14","country_code":"US","type":"education","lineage":["https://openalex.org/I103163165"]}],"countries":["US"],"is_corresponding":true,"raw_author_name":"Chris Zimmer","raw_affiliation_strings":["Florida State University"],"affiliations":[{"raw_affiliation_string":"Florida State University","institution_ids":["https://openalex.org/I103163165"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5065090483","display_name":"Stephen Hines","orcid":null},"institutions":[{"id":"https://openalex.org/I103163165","display_name":"Florida State University","ror":"https://ror.org/05g3dte14","country_code":"US","type":"education","lineage":["https://openalex.org/I103163165"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Stephen Roderick Hines","raw_affiliation_strings":["Florida State University"],"affiliations":[{"raw_affiliation_string":"Florida State University","institution_ids":["https://openalex.org/I103163165"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5111980656","display_name":"Prasad A. Kulkarni","orcid":null},"institutions":[{"id":"https://openalex.org/I103163165","display_name":"Florida State University","ror":"https://ror.org/05g3dte14","country_code":"US","type":"education","lineage":["https://openalex.org/I103163165"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Prasad Kulkarni","raw_affiliation_strings":["Florida State University"],"affiliations":[{"raw_affiliation_string":"Florida State University","institution_ids":["https://openalex.org/I103163165"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5004937273","display_name":"Gary Tyson","orcid":"https://orcid.org/0009-0002-5081-2843"},"institutions":[{"id":"https://openalex.org/I103163165","display_name":"Florida State University","ror":"https://ror.org/05g3dte14","country_code":"US","type":"education","lineage":["https://openalex.org/I103163165"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Gary Tyson","raw_affiliation_strings":["Florida State University"],"affiliations":[{"raw_affiliation_string":"Florida State University","institution_ids":["https://openalex.org/I103163165"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5108249713","display_name":"David Whalley","orcid":null},"institutions":[{"id":"https://openalex.org/I103163165","display_name":"Florida State University","ror":"https://ror.org/05g3dte14","country_code":"US","type":"education","lineage":["https://openalex.org/I103163165"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"David Whalley","raw_affiliation_strings":["Florida State University"],"affiliations":[{"raw_affiliation_string":"Florida State University","institution_ids":["https://openalex.org/I103163165"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":5,"corresponding_author_ids":["https://openalex.org/A5037422850"],"corresponding_institution_ids":["https://openalex.org/I103163165"],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":0,"citation_normalized_percentile":{"value":0.11228976,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":null,"issue":null,"first_page":"165","last_page":"169"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9994000196456909,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9994000196456909,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10260","display_name":"Software Engineering Research","score":0.9747999906539917,"subfield":{"id":"https://openalex.org/subfields/1710","display_name":"Information Systems"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T12127","display_name":"Software System Performance and Reliability","score":0.9745000004768372,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.8809654712677002},{"id":"https://openalex.org/keywords/register-allocation","display_name":"Register allocation","score":0.8731327056884766},{"id":"https://openalex.org/keywords/compiler","display_name":"Compiler","score":0.81396484375},{"id":"https://openalex.org/keywords/software-pipelining","display_name":"Software pipelining","score":0.7295536398887634},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.6912739276885986},{"id":"https://openalex.org/keywords/optimizing-compiler","display_name":"Optimizing compiler","score":0.6501505970954895},{"id":"https://openalex.org/keywords/program-optimization","display_name":"Program optimization","score":0.5571728944778442},{"id":"https://openalex.org/keywords/loop-optimization","display_name":"Loop optimization","score":0.5312910676002502},{"id":"https://openalex.org/keywords/register-file","display_name":"Register file","score":0.4696238338947296},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.4619849622249603},{"id":"https://openalex.org/keywords/software","display_name":"Software","score":0.46041542291641235},{"id":"https://openalex.org/keywords/code-generation","display_name":"Code generation","score":0.4350664019584656},{"id":"https://openalex.org/keywords/instruction-scheduling","display_name":"Instruction scheduling","score":0.41994738578796387},{"id":"https://openalex.org/keywords/instruction-set","display_name":"Instruction set","score":0.3785221576690674},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.3616172671318054},{"id":"https://openalex.org/keywords/programming-language","display_name":"Programming language","score":0.23094874620437622},{"id":"https://openalex.org/keywords/operating-system","display_name":"Operating system","score":0.15385261178016663},{"id":"https://openalex.org/keywords/dynamic-priority-scheduling","display_name":"Dynamic priority scheduling","score":0.1112353503704071},{"id":"https://openalex.org/keywords/schedule","display_name":"Schedule","score":0.09062498807907104}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.8809654712677002},{"id":"https://openalex.org/C128916667","wikidata":"https://www.wikidata.org/wiki/Q1343660","display_name":"Register allocation","level":3,"score":0.8731327056884766},{"id":"https://openalex.org/C169590947","wikidata":"https://www.wikidata.org/wiki/Q47506","display_name":"Compiler","level":2,"score":0.81396484375},{"id":"https://openalex.org/C188854837","wikidata":"https://www.wikidata.org/wiki/Q268469","display_name":"Software pipelining","level":3,"score":0.7295536398887634},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.6912739276885986},{"id":"https://openalex.org/C190902152","wikidata":"https://www.wikidata.org/wiki/Q1325106","display_name":"Optimizing compiler","level":3,"score":0.6501505970954895},{"id":"https://openalex.org/C139571649","wikidata":"https://www.wikidata.org/wiki/Q1156793","display_name":"Program optimization","level":3,"score":0.5571728944778442},{"id":"https://openalex.org/C29331672","wikidata":"https://www.wikidata.org/wiki/Q3354468","display_name":"Loop optimization","level":4,"score":0.5312910676002502},{"id":"https://openalex.org/C117280010","wikidata":"https://www.wikidata.org/wiki/Q180944","display_name":"Register file","level":3,"score":0.4696238338947296},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.4619849622249603},{"id":"https://openalex.org/C2777904410","wikidata":"https://www.wikidata.org/wiki/Q7397","display_name":"Software","level":2,"score":0.46041542291641235},{"id":"https://openalex.org/C133162039","wikidata":"https://www.wikidata.org/wiki/Q1061077","display_name":"Code generation","level":3,"score":0.4350664019584656},{"id":"https://openalex.org/C73564150","wikidata":"https://www.wikidata.org/wiki/Q11417093","display_name":"Instruction scheduling","level":5,"score":0.41994738578796387},{"id":"https://openalex.org/C202491316","wikidata":"https://www.wikidata.org/wiki/Q272683","display_name":"Instruction set","level":2,"score":0.3785221576690674},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.3616172671318054},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.23094874620437622},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.15385261178016663},{"id":"https://openalex.org/C107568181","wikidata":"https://www.wikidata.org/wiki/Q5319000","display_name":"Dynamic priority scheduling","level":3,"score":0.1112353503704071},{"id":"https://openalex.org/C68387754","wikidata":"https://www.wikidata.org/wiki/Q7271585","display_name":"Schedule","level":2,"score":0.09062498807907104},{"id":"https://openalex.org/C26517878","wikidata":"https://www.wikidata.org/wiki/Q228039","display_name":"Key (lock)","level":2,"score":0.0},{"id":"https://openalex.org/C119948110","wikidata":"https://www.wikidata.org/wiki/Q7858726","display_name":"Two-level scheduling","level":4,"score":0.0}],"mesh":[],"locations_count":2,"locations":[{"id":"doi:10.1145/1289881.1289912","is_oa":false,"landing_page_url":"https://doi.org/10.1145/1289881.1289912","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 2007 international conference on Compilers, architecture, and synthesis for embedded systems","raw_type":"proceedings-article"},{"id":"pmh:oai:CiteSeerX.psu:10.1.1.413.8848","is_oa":false,"landing_page_url":"http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.413.8848","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"http://www.cecs.uci.edu/~papers/esweek07/cases/p165.pdf","raw_type":"text"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":19,"referenced_works":["https://openalex.org/W1967022475","https://openalex.org/W1969648707","https://openalex.org/W2012512596","https://openalex.org/W2032094184","https://openalex.org/W2034402701","https://openalex.org/W2074610898","https://openalex.org/W2105605502","https://openalex.org/W2107802282","https://openalex.org/W2123412205","https://openalex.org/W2157758640","https://openalex.org/W2162208256","https://openalex.org/W2543996155","https://openalex.org/W2576288252","https://openalex.org/W4232919122","https://openalex.org/W4238321249","https://openalex.org/W4252143594","https://openalex.org/W4285719527","https://openalex.org/W6606251058","https://openalex.org/W7037444635"],"related_works":["https://openalex.org/W18945967","https://openalex.org/W2045503187","https://openalex.org/W2136520452","https://openalex.org/W1513982523","https://openalex.org/W2145456033","https://openalex.org/W3013660549","https://openalex.org/W4244928472","https://openalex.org/W2152533950","https://openalex.org/W2372015459","https://openalex.org/W2103250493"],"abstract_inverted_index":{"Aggressive":[0],"compiler":[1],"optimizations":[2,49,79],"such":[3],"as":[4,58,152,154],"software":[5,130,164],"pipelining":[6,131],"and":[7,108,132],"loop":[8,36,133],"invariant":[9,134],"code":[10,135],"motion":[11,136],"can":[12,70,122],"significantly":[13],"improve":[14],"application":[15,76,128],"performance,":[16],"but":[17],"these":[18,48,78,95],"transformations":[19],"often":[20,44],"require":[21],"the":[22,75,127,149,171],"use":[23],"of":[24,77,129,140,161,174],"several":[25],"additional":[26],"registers":[27,62],"to":[28,73,81,99,125,145,166],"hold":[29],"data":[30],"values":[31],"across":[32],"one":[33],"or":[34],"more":[35],"iterations.":[37],"Compilers":[38],"that":[39,93,117],"target":[40],"embedded":[41,52,141,150,162],"systems":[42,53,163],"may":[43],"have":[45,57],"difficulty":[46],"exploiting":[47],"since":[50],"many":[51,59],"typically":[54],"do":[55],"not":[56],"general":[60],"purpose":[61],"available.":[63],"Alternate":[64],"register":[65,68,97,172],"structures":[66,98],"like":[67],"queues":[69],"be":[71,100,123],"used":[72,124],"facilitate":[74,126],"due":[80,165],"common":[82],"reference":[83],"patterns.":[84],"In":[85],"this":[86,118],"paper,":[87],"we":[88],"propose":[89],"a":[90,104,138,167],"microarchitectural":[91],"technique":[92,121],"permits":[94],"alternate":[96],"efficiently":[101],"mapped":[102],"into":[103],"given":[105],"processor":[106],"architecture":[107],"automatically":[109],"exploited":[110],"by":[111],"an":[112],"optimizing":[113],"compiler.":[114],"We":[115],"show":[116],"minimally":[119],"invasive":[120],"for":[137,148,157],"variety":[139],"benchmarks.":[142],"This":[143],"leads":[144],"performance":[146],"improvements":[147],"processor,":[151],"well":[153],"new":[155],"opportunities":[156],"further":[158],"aggressive":[159],"optimization":[160],"significant":[168],"decrease":[169],"in":[170],"pressure":[173],"tight":[175],"loops.":[176]},"counts_by_year":[],"updated_date":"2026-04-04T16:13:02.066488","created_date":"2025-10-10T00:00:00"}